公开(公告)号：US11329058B2

公开(公告)日：2022-05-10

申请号：US17087419

申请日：2020-11-02

Applicant: Micron Technology, Inc.

Inventor： Aaron S. Yip

IPC: H01L27/1159 ,  H01L27/11529 ,  H01L27/11582 ,  H01L27/11573 ,  H01L27/11556 ,  H01L27/11519 ,  H01L27/11575 ,  H01L27/11565 ,  H01L27/11548 ,  H01L27/1157 ,  H01L27/11524

Abstract: A microelectronic device comprises a stack structure having tiers each including a conductive structure and an insulating structure, the stack structure comprises a staircase region comprising staircase structures, a select gate contact region, and a memory array region between the staircase region and the select gate contact region; contact structures on steps of the staircase structures; string drivers coupled to the contact structures and comprising transistors underlying and within horizontal boundaries of the staircase region; a triple well structure underlying the memory array region; a select gate structure between the stack structure and the triple well structure; semiconductive pillar structures within horizontal boundaries of the memory array region and extending through the stack structure and the select gate structure to the triple well structure; and a select gate contact structure within horizontal boundaries of the select gate contact region and extending through the stack structure to the select gate structure.

公开(公告)号：US11094357B2

公开(公告)日：2021-08-17

申请号：US16405072

申请日：2019-05-07

Applicant: Micron Technology, Inc.

Inventor： Aaron S. Yip ,  Theodore T. Pekny

IPC: G11C16/06 ,  G11C8/08 ,  G11C16/26 ,  G11C16/08 ,  G11C16/04

Abstract: A memory device includes a memory array with memory blocks each having a plurality of memory cells, and one or more current monitors configured to measure current during post-deployment operation of the memory device; and a controller configured to identify a bad block within the memory blocks based on the measured current, and disable the bad block for preventing access thereof during subsequent operations of the memory device.

公开(公告)号：US10535408B2

公开(公告)日：2020-01-14

申请号：US16427587

申请日：2019-05-31

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Aaron S. Yip

IPC: G11C16/04 ,  G11C16/14 ,  G11C16/34 ,  G11C16/26

Abstract: Memories having a controller configured to apply a first voltage level to channel regions of memory cells of an array of memory cells coupled to a plurality of access lines; apply a second voltage level, lower than the first voltage level, to a first access line; apply a third voltage level, lower than the second voltage level, to a second access line while applying the second voltage level to the first access line and while applying the first voltage level to the channel regions of the memory cells; and increase the voltage level applied to the second access line to the second voltage level and decrease the voltage level applied to the first access line to a fourth voltage level, lower than the second voltage level and different than the third voltage level, while applying the first voltage level to the channel regions of the memory cells.

公开(公告)号：US10332603B2

公开(公告)日：2019-06-25

申请号：US15869501

申请日：2018-01-12

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Benjamin Louie ,  Ali Mohammadzadeh ,  Aaron S. Yip

IPC: G11C16/24 ,  G11C16/04 ,  G11C16/06 ,  G11C16/08 ,  G11C16/10 ,  G11C16/14 ,  G11C16/26

Abstract: Memory devices including an array of memory cells, a plurality of access lines selectively coupled to respective pluralities of memory cells of the array of memory cells, a plurality of first registers, a second register, a first multiplexer, a second multiplexer, and a decoder configured to selectively connect a corresponding access line to a selected voltage source of a plurality of voltage sources in response to the output of the second multiplexer, wherein the second multiplexer is configured to pass a selected one of the output of the second register and the output of the first multiplexer to its output, and wherein the first multiplexer is configured to pass a selected one of the outputs of the plurality of first registers to its output.

公开(公告)号：US10332601B2

公开(公告)日：2019-06-25

申请号：US15687581

申请日：2017-08-28

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Aaron S. Yip

IPC: G11C16/04 ,  G11C16/14 ,  G11C16/26

Abstract: Methods include applying a first voltage to channel regions of a plurality of memory cells; applying a lower second voltage to each access line of a plurality of access lines coupled to the memory cells other than a first set of access lines; applying a lower third voltage to the first set of access lines while applying the first voltage and the second voltage; determining a desired voltage level of the third voltage for a subsequent set of access lines; and applying the third voltage to the subsequent set of access lines while applying the first voltage and while applying the second voltage to each access line of the plurality of access lines other than the subsequent set of access lines. Methods further include methods of determining the desired voltage level for the third voltage for each set of access lines.

公开(公告)号：US09767909B1

公开(公告)日：2017-09-19

申请号：US15072954

申请日：2016-03-17

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Aaron S. Yip

IPC: G11C11/34 ,  G11C16/04 ,  G11C16/10 ,  G11C16/26

CPC classification number: G11C16/10 ,  G11C11/5628 ,  G11C16/0483 ,  G11C16/26

Abstract: Methods of operating a memory include determining indications of programming voltages sufficient to program respective groups of memory cells of a plurality of groups of memory cells to a particular range of threshold voltages, applying a stepped programming pulse to a selected access line connected to each memory cell of the plurality of groups of memory cells, and enabling each group of memory cells for programming when a voltage level of the stepped programming pulse corresponds to the respective indication of the programming voltage sufficient to program that group of memory cells to the particular range of threshold voltages.

公开(公告)号：US09589978B1

公开(公告)日：2017-03-07

申请号：US15053291

申请日：2016-02-25

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Aaron S. Yip

IPC: H01L27/108 ,  H01L27/115 ,  H01L23/528

CPC classification number: H01L27/11573 ,  H01L23/528 ,  H01L27/11526 ,  H01L27/11548 ,  H01L27/11556 ,  H01L27/11575 ,  H01L27/11582

Abstract: In an example, a memory device includes a staircase comprising a flight of stairs and a plurality of pass transistors directly under the staircase. The stairs of the flight of stairs are respectively coupled to different tiers of memory cells, and a different pass transistor of the plurality of pass transistors is coupled to each of the stairs of the flight of stairs.

Abstract translation: 在一个例子中，存储装置包括一个阶梯，其阶梯和楼梯下的多个通过晶体管。 楼梯的楼梯分别耦合到不同级别的存储器单元，并且多个通过晶体管中的不同的通过晶体管被耦合到楼梯的每个楼梯。

公开(公告)号：US20160086672A1

公开(公告)日：2016-03-24

申请号：US14958217

申请日：2015-12-03

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Benjamin Louie ,  Ali Mohammadzadeh ,  Aaron S. Yip

IPC: G11C16/24 ,  G11C16/14 ,  G11C16/26 ,  G11C16/08

CPC classification number: G11C16/24 ,  G11C16/0483 ,  G11C16/06 ,  G11C16/08 ,  G11C16/10 ,  G11C16/14 ,  G11C16/26

Abstract: Memory devices and methods are disclosed, such as devices configured to store a number of access line biasing patterns to be applied during a memory device operation performed on a particular row of memory cells in the memory device. Memory devices are further configured to support modification of the stored bias patterns, providing flexibility in biasing access lines through changes to the bias patterns stored in the memory device. Methods and devices further facilitate performing memory device operations under multiple biasing conditions to evaluate and characterize the memory device by adjustment of the stored bias patterns without requiring an associated hardware change to the memory device.

Abstract translation: 公开了存储器件和方法，诸如被配置为存储在对存储器件中的特定行存储器单元执行的存储器件操作期间要施加的多个访问线偏置模式的器件。 存储器设备被进一步配置为支持所存储的偏置图案的修改，通过对存储在存储器件中的偏置图案的改变来偏置访问线路提供灵活性。 方法和设备进一步便于在多个偏置条件下执行存储器件操作，以通过调整存储的偏压图案来评估和表征存储器件，而不需要对存储器件的相关联的硬件改变。

公开(公告)号：US09251860B2

公开(公告)日：2016-02-02

申请号：US14735350

申请日：2015-06-10

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Aaron S. Yip ,  Mark A. Helm ,  Ramin Ghodsi

IPC: G11C16/00 ,  G11C5/02 ,  G11C5/06 ,  G11C16/04

CPC classification number: G11C5/025 ,  G11C5/063 ,  G11C8/08 ,  G11C11/06035 ,  G11C11/06064 ,  G11C11/063 ,  G11C16/02 ,  G11C16/0483 ,  H01L27/11531 ,  H01L27/11573 ,  Y10T29/49069

Abstract: In an embodiment, a memory device includes a stack of tiers of memory cells, a tier of local devices at a level above the stack of tiers of memory cells, and a tier of global devices at substantially a same level as the tier of local devices. A local device may provide selective access to a data line. A global device may provide selective access to a global access line. A tier of memory cells may be selectively coupled to a global access line by the global device of the tier of global devices.

公开(公告)号：US09070442B2

公开(公告)日：2015-06-30

申请号：US14013370

申请日：2013-08-29

Applicant: Micron Technology, Inc.

Inventor： Aaron S. Yip ,  Mark A. Helm ,  Ramin Ghodsi

IPC: G11C16/00 ,  G11C16/02 ,  G11C11/063 ,  G11C11/06 ,  G11C5/02

CPC classification number: G11C5/025 ,  G11C5/063 ,  G11C8/08 ,  G11C11/06035 ,  G11C11/06064 ,  G11C11/063 ,  G11C16/02 ,  G11C16/0483 ,  H01L27/11531 ,  H01L27/11573 ,  Y10T29/49069

Abstract: In an embodiment, a memory device includes a stack of tiers of memory cells, a tier of local devices at a level above the stack of tiers of memory cells, and a tier of global devices at substantially a same level as the tier of local devices. A local device may provide selective access to a data line. A global device may provide selective access to a global access line. A tier of memory cells may be selectively coupled to a global access line by the global device of the tier of global devices.

Abstract translation: 在一个实施例中，存储器设备包括层级的存储器单元的堆叠，位于存储器单元的层级之上的层级的本地设备层，以及与本地设备层基本相同的级别的全球设备层 。 本地设备可以提供对数据线的选择性访问。 全局设备可以提供对全局接入线的选择性访问。 一层存储器单元可以由全球设备层的全局设备选择性地耦合到全局接入线路。