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    MEMORY PLATE SEGMENTATION TO REDUCE OPERATING POWER
    62.
    发明申请
    MEMORY PLATE SEGMENTATION TO REDUCE OPERATING POWER 审中-公开

    公开(公告)号：US20190027204A1

    公开(公告)日：2019-01-24

    申请号：US15655675

    申请日：2017-07-20

    Applicant: Micron Technology, Inc.

    Inventor： Tae H. Kim ,  Corrado Villa

    IPC: G11C11/22 ,  G06F1/32

    CPC classification number: G11C11/2297 ,  G06F1/3275 ,  G06F1/3287 ,  G06F1/3296 ,  G11C11/221 ,  G11C11/2255 ,  G11C11/2257 ,  G11C11/2273 ,  G11C11/2275

    Abstract: Methods, systems, and devices for operating a ferroelectric memory cell or cells are described. An electronic memory device may include a plurality of plate portions separated by a plurality of segmentation lines, which may be oriented in a plane parallel to rows of a memory array or columns of the memory array, or both. The segmented plate may be employed instead of a single plate for the array. The one or more plate portions may be energized during access operations of a ferroelectric cell in order to create a voltage different across the cell or to facilitate changing the charge of the cell. Each of the plate portions may include one or more memory cells. The memory cells on a plate portion may be read from or written to after the plate portion is activated by a plate driver.

    Apparatuses and methods for memory operations having variable latencies
    64.
    发明授权
    Apparatuses and methods for memory operations having variable latencies 有权

    公开(公告)号：US10067764B2

    公开(公告)日：2018-09-04

    申请号：US15646874

    申请日：2017-07-11

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： Graziano Mirichigni ,  Corrado Villa ,  Luca Porzio ,  Chee Weng Tan ,  Sebastien Lemarie ,  Andre Klindworth

    IPC: G06F13/16 ,  G11C7/10 ,  G11C7/22 ,  G11C13/00 ,  G06F9/30

    Abstract: Apparatuses and methods for performing memory operations are described. An example apparatus includes a memory operation controller. The memory operation controller is configured to receive memory instructions and decode the same to provide internal signals for performing memory operations for the memory instructions. The memory operation controller is further configured to provide information indicative of a time for a variable latency period of a memory instruction during the variable latency period. In an example method, a write instruction and an address to which write data is to be written is received at a memory and an acknowledgement indicative of an end of a variable latency period for the write instruction is provided. After waiting a variable bus turnaround after the acknowledgement, write data for the write instruction is received.

    Error correction code for unidirectional memory
    68.
    发明授权
    Error correction code for unidirectional memory 有权
    单向存储器的纠错码

    公开(公告)号：US09124301B2

    公开(公告)日：2015-09-01

    申请号：US13846538

    申请日：2013-03-18

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： Christophe Laurent ,  Paolo Amato ,  Marco Sforzin ,  Corrado Villa

    IPC: G11C29/00 ,  H03M13/29 ,  G06F11/10

    CPC classification number: G06F11/1068 ,  G11C29/52 ,  H03M13/2909

    Abstract: A memory array and a method of writing to a unidirectional non-volatile storage cell are disclosed whereby a user data word is transformed to an internal data word and written to one or more unidirectional data storage cells according to a cell coding scheme. A check word may be generated that corresponds to the internal data word. In some embodiments, the check word may be generated by inverting one or more bits of an intermediate check word. Other embodiments may be described and claimed.

    Abstract translation: 公开了一种写入单向非易失性存储单元的存储器阵列和方法，其中用户数据字被转换为内部数据字，并根据小区编码方案写入一个或多个单向数据存储单元。 可以生成对应于内部数据字的检查字。 在一些实施例中，可以通过反转中间检查字的一个或多个位来产生检验字。 可以描述和要求保护其他实施例。

    APPARATUSES AND METHODS FOR MEMORY OPERATIONS HAVING VARIABLE LATENCIES
    69.
    发明申请
    APPARATUSES AND METHODS FOR MEMORY OPERATIONS HAVING VARIABLE LATENCIES 有权
    具有可变延迟的存储器操作的装置和方法

    公开(公告)号：US20140122814A1

    公开(公告)日：2014-05-01

    申请号：US13840929

    申请日：2013-03-15

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： Graziano Mirichigni ,  Corrado Villa ,  Luca Porzio ,  Chee Weng Tan ,  Sebastien Lemarie ,  Andre Klindworth

    IPC: G06F9/30

    CPC classification number: G06F9/30047 ,  G06F13/161 ,  G06F13/1689 ,  G11C7/1063 ,  G11C7/22 ,  G11C13/0004 ,  G11C13/004 ,  G11C13/0061 ,  G11C13/0069 ,  G11C2207/2272

    Abstract: Apparatuses and methods for performing memory operations are described. An example apparatus includes a memory operation controller. The memory operation controller is configured to receive memory instructions and decode the same to provide internal signals for performing memory operations for the memory instructions. The memory operation controller is further configured to provide information indicative of a time for a variable latency period of a memory instruction during the variable latency period. In an example method, a write instruction and an address to which write data is to be written is received at a memory and an acknowledgement indicative of an end of a variable latency period for the write instruction is provided. After waiting a variable bus turnaround after the acknowledgement, write data for the write instruction is received.

    Abstract translation: 描述用于执行存储器操作的装置和方法。 示例性装置包括存储器操作控制器。 存储器操作控制器被配置为接收存储器指令并对其进行解码以提供用于对存储器指令执行存储器操作的内部信号。 存储器操作控制器还被配置为在可变等待时间周期期间提供指示存储器指令的可变等待时间周期的时间的信息。 在示例性方法中，在存储器处接收要写入数据的写指令和地址，并且提供指示用于写指令的可变等待时间周期结束的确认。 在确认之后等待可变总线周转后，接收写入指令的写入数据。

    DECODER ARCHITECTURE FOR MEMORY DEVICE
    70.
    发明申请
    DECODER ARCHITECTURE FOR MEMORY DEVICE 有权

    公开(公告)号：US20250014640A1

    公开(公告)日：2025-01-09

    申请号：US18768922

    申请日：2024-07-10

    Applicant: Micron Technology, Inc.

    Inventor： Ferdinando Bedeschi ,  Jeffrey E. Koelling ,  Hari Giduturi ,  Riccardo Muzzetto ,  Corrado Villa

    IPC: G11C13/00

    Abstract: Methods, systems, and devices for decoder architecture for memory device are described. An apparatus includes a memory array having a memory cell and an access line coupled with the cell and a decoder having a first stage and a second stage. The decoder supplying a first voltage during a first access operation and a second voltage during a second access operation to the access line. The second stage of the decoder includes a first transistor that supplies the first voltage based on a third voltage at the source of the first transistor exceeding a fourth voltage at a gate of the first transistor and a first threshold voltage. The second stage includes a second transistor that supplies the second voltage based on a fifth voltage at a gate of the second transistor exceeding a sixth voltage at the source of the second transistor and a second threshold voltage.

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