公开(公告)号：US20190013329A1

公开(公告)日：2019-01-10

申请号：US16111762

申请日：2018-08-24

Applicant: Micron Technology, Inc.

Inventor： Zhenyu Lu ,  Roger W. Lindsay ,  Akira Goda ,  John Hopkins

IPC: H01L27/11582 ,  H01L21/02 ,  G11C16/26 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11524 ,  G11C16/34 ,  G11C16/04 ,  H01L27/11573 ,  H01L27/11529 ,  G11C16/14

CPC classification number: H01L27/11582 ,  G11C16/04 ,  G11C16/0475 ,  G11C16/0483 ,  G11C16/14 ,  G11C16/26 ,  G11C16/3445 ,  H01L21/02178 ,  H01L27/11524 ,  H01L27/11529 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11573

Abstract: Some embodiments include apparatuses and methods having multiple decks of memory cells and associated control gates. A method includes forming a first deck having alternating conductor materials and dielectric materials and a hole containing materials extending through the conductor materials and the dielectric materials. The methods can also include forming a sacrificial material in an enlarged portion of the hole and forming a second deck of memory cells over the first deck. Additional apparatuses and methods are described.

公开(公告)号：US20180350827A1

公开(公告)日：2018-12-06

申请号：US15980503

申请日：2018-05-15

Applicant: Micron Technology, Inc.

Inventor： Charles H. Dennison ,  Akira Goda ,  John Hopkins ,  Fatma Arzum Simsek-Ege ,  Krishna K. Parat

IPC: H01L27/11556 ,  H01L29/66 ,  H01L27/11578 ,  H01L21/28

CPC classification number: H01L27/11556 ,  H01L21/28273 ,  H01L27/11578 ,  H01L29/66666 ,  H01L29/66825 ,  H01L29/66833

Abstract: Floating gate memory cells in vertical memory. A control gate is formed between a first tier of dielectric material and a second tier of dielectric material. A floating gate is formed between the first tier of dielectric material and the second tier of dielectric material, wherein the floating gate includes a protrusion extending towards the control gate. A charge blocking structure is formed between the floating gate and the control gate, wherein at least a portion of the charge blocking structure wraps around the protrusion.

公开(公告)号：US10090317B2

公开(公告)日：2018-10-02

申请号：US15221131

申请日：2016-07-27

Applicant: Micron Technology, Inc.

Inventor： Jie Sun ,  Zhenyu Lu ,  Roger W. Lindsay ,  Brian Cleereman ,  John Hopkins ,  Hongbin Zhu ,  Fatma Arzum Simsek-Ege ,  Prasanna Srinivasan ,  Purnima Narayanan

IPC: H01L21/3205 ,  H01L27/11582 ,  H01L27/11556 ,  H01L27/11524 ,  H01L29/66 ,  H01L29/788 ,  G11C16/04 ,  H01L27/1157

Abstract: Methods for forming a string of memory cells, apparatuses having a string of memory cells, and systems are disclosed. One such method for forming a string of memory cells forms a source material over a substrate. A capping material may be formed over the source material. A select gate material may be formed over the capping material. A plurality of charge storage structures may be formed over the select gate material in a plurality of alternating levels of control gate and insulator materials. A first opening may be formed through the plurality of alternating levels of control gate and insulator materials, the select gate material, and the capping material. A channel material may be formed along the sidewall of the first opening. The channel material has a thickness that is less than a width of the first opening, such that a second opening is formed by the semiconductor channel material.

公开(公告)号：US10079246B2

公开(公告)日：2018-09-18

申请号：US15849242

申请日：2017-12-20

Applicant: Micron Technology, Inc.

Inventor： Zhenyu Lu ,  Roger W. Lindsay ,  Akira Goda ,  John Hopkins

IPC: H01L21/336 ,  H01L27/11582 ,  G11C16/04 ,  G11C16/14 ,  H01L27/11573 ,  G11C16/26 ,  H01L27/11529 ,  H01L27/11524 ,  H01L21/02 ,  H01L27/1157 ,  G11C16/34 ,  H01L27/11556

CPC classification number: H01L27/11582 ,  G11C16/04 ,  G11C16/0475 ,  G11C16/0483 ,  G11C16/14 ,  G11C16/26 ,  G11C16/3445 ,  H01L21/02178 ,  H01L27/11524 ,  H01L27/11529 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11573

Abstract: Some embodiments include apparatuses and methods having multiple decks of memory cells and associated control gates. A method includes forming a first deck having alternating conductor materials and dielectric materials and a hole containing materials extending through the conductor materials and the dielectric materials. The methods can also include forming a sacrificial material in an enlarged portion of the hole and forming a second deck of memory cells over the first deck. Additional apparatuses and methods are described.

公开(公告)号：US20180138196A1

公开(公告)日：2018-05-17

申请号：US15849242

申请日：2017-12-20

Applicant: Micron Technology, Inc.

Inventor： Zhenyu Lu ,  Roger W. Lindsay ,  Akira Goda ,  John Hopkins

IPC: H01L27/11582 ,  G11C16/04 ,  G11C16/14 ,  H01L27/11573 ,  H01L27/11556 ,  H01L27/11529 ,  H01L27/11524 ,  H01L21/02 ,  H01L27/1157 ,  G11C16/34 ,  G11C16/26

CPC classification number: H01L27/11582 ,  G11C16/04 ,  G11C16/0475 ,  G11C16/0483 ,  G11C16/14 ,  G11C16/26 ,  G11C16/3445 ,  H01L21/02178 ,  H01L27/11524 ,  H01L27/11529 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11573

Abstract: Some embodiments include apparatuses and methods having multiple decks of memory cells and associated control gates. A method includes forming a first deck having alternating conductor materials and dielectric materials and a hole containing materials extending through the conductor materials and the dielectric materials. The methods can also include forming a sacrificial material in an enlarged portion of the hole and forming a second deck of memory cells over the first deck. Additional apparatuses and methods are described.

公开(公告)号：US09853046B2

公开(公告)日：2017-12-26

申请号：US15174478

申请日：2016-06-06

Applicant: Micron Technology, Inc.

Inventor： Zhenyu Lu ,  Roger W. Lindsay ,  Akira Goda ,  John Hopkins

IPC: H01L29/76 ,  H01L27/11582 ,  G11C16/14 ,  G11C16/34 ,  H01L27/11524 ,  H01L27/1157 ,  H01L27/11556 ,  H01L21/02 ,  G11C16/26 ,  G11C16/04 ,  H01L27/11529 ,  H01L27/11573

CPC classification number: H01L27/11582 ,  G11C16/04 ,  G11C16/0475 ,  G11C16/0483 ,  G11C16/14 ,  G11C16/26 ,  G11C16/3445 ,  H01L21/02178 ,  H01L27/11524 ,  H01L27/11529 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11573

Abstract: Some embodiments include apparatuses and methods having multiple decks of memory cells and associated control gates. A method includes forming a first deck having alternating conductor materials and dielectric materials and a hole containing materials extending through the conductor materials and the dielectric materials. The methods can also include forming a sacrificial material in an enlarged portion of the hole and forming a second deck of memory cells over the first deck. Additional apparatuses and methods are described.

公开(公告)号：US20170365615A1

公开(公告)日：2017-12-21

申请号：US15691477

申请日：2017-08-30

Applicant: Micron Technology, Inc.

Inventor： Charles H. Dennison ,  Akira Goda ,  John Hopkins ,  Fatma Arzum Simsek-Ege ,  Krishna K. Parat

IPC: H01L27/11556 ,  H01L21/28 ,  H01L27/11578 ,  H01L29/66

CPC classification number: H01L27/11556 ,  H01L21/28273 ,  H01L27/11578 ,  H01L29/66666 ,  H01L29/66825 ,  H01L29/66833

Abstract: Floating gate memory cells in vertical memory. A control gate is formed between a first tier of dielectric material and a second tier of dielectric material. A floating gate is formed between the first tier of dielectric material and the second tier of dielectric material, wherein the floating gate includes a protrusion extending towards the control gate. A charge blocking structure is formed between the floating gate and the control gate, wherein at least a portion of the charge blocking structure wraps around the protrusion.

公开(公告)号：US20160351580A1

公开(公告)日：2016-12-01

申请号：US14722824

申请日：2015-05-27

Applicant: Micron Technology, Inc.

Inventor： John Hopkins ,  Darwin Franseda Fan

IPC: H01L27/115 ,  H01L29/49 ,  H01L21/311 ,  H01L29/788 ,  H01L21/28 ,  H01L21/02

CPC classification number: H01L29/4916 ,  H01L21/28273 ,  H01L27/11556 ,  H01L29/42324 ,  H01L29/7883

Abstract: Protective dielectrics are discussed generally herein. In one or more embodiments, a three-dimensional vertical memory may include a protective dielectric material. A device may include an etch stop material, a first control gate (CG) over the etch stop material, a first CG recess adjacent the first CG, a trench adjacent the first CG recess, and an at least partially oxidized polysilicon on at least a portion of the etch stop material. The at least partially oxidized polysilicon may line a sidewall of the trench and may line the first CG recess.

Abstract translation: 本文一般讨论保护电介质。 在一个或多个实施例中，三维垂直存储器可以包括保护电介质材料。 器件可以包括蚀刻停止材料，蚀刻停止材料上方的第一控制栅极（CG），与第一CG相邻的第一CG凹槽，与第一CG凹槽相邻的沟槽，以及至少部分氧化的多晶硅 蚀刻停止材料的一部分。 至少部分氧化的多晶硅可以在沟槽的侧壁上划线，并且可以使第一CG凹槽成线。

公开(公告)号：US09184175B2

公开(公告)日：2015-11-10

申请号：US13838297

申请日：2013-03-15

Applicant: Micron Technology, Inc.

Inventor： Charles H. Dennison ,  Akira Goda ,  John Hopkins ,  Fatma Arzum Simsek-Ege ,  Krishna K. Parat

IPC: H01L29/788 ,  H01L27/115 ,  H01L29/66

CPC classification number: H01L27/11556 ,  H01L21/28273 ,  H01L27/11578 ,  H01L29/66666 ,  H01L29/66825 ,  H01L29/66833

Abstract: Floating gate memory cells in vertical memory. A control gate is formed between a first tier of dielectric material and a second tier of dielectric material. A floating gate is formed between the first tier of dielectric material and the second tier of dielectric material, wherein the floating gate includes a protrusion extending towards the control gate. A charge blocking structure is formed between the floating gate and the control gate, wherein at least a portion of the charge blocking structure wraps around the protrusion.

Abstract translation: 垂直存储器中的浮动存储单元。 控制栅极形成在介电材料的第一层和第二层电介质材料之间。 浮动栅极形成在介电材料的第一层和第二层介质材料之间，其中浮动栅极包括朝向控制栅极延伸的突起。 在浮置栅极和控制栅极之间形成电荷阻挡结构，其中电荷阻挡结构的至少一部分围绕突起卷绕。

公开(公告)号：US20150287734A1

公开(公告)日：2015-10-08

申请号：US14746515

申请日：2015-06-22

Applicant: Micron Technology, Inc.

Inventor： Fatma Arzum Simsek-Ege ,  John Hopkins ,  Srikant Jayanti

IPC: H01L27/115

CPC classification number: H01L27/11556 ,  H01L27/11524 ,  H01L27/11582 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7889 ,  H01L29/7926

Abstract: Vertical memories and methods of making the same are discussed generally herein. In one embodiment, a vertical memory can include a vertical pillar extending to a source, an etch stop tier over the source, and a stack of alternating dielectric tiers and conductive tiers over the etch stop tier. The etch stop tier can comprise a blocking dielectric adjacent to the pillar. In another embodiment, the etch stop tier can comprise a blocking dielectric adjacent to the pillar, and a plurality of dielectric films horizontally extending from the blocking dielectric into the etch stop tier.

Abstract translation: 垂直记忆及其制备方法一般在此讨论。 在一个实施例中，垂直存储器可以包括延伸到源的垂直柱，源极上的蚀刻停止层，以及蚀刻停止层上方的交替介电层和导电层的堆叠。 蚀刻停止层可以包括邻近柱的阻挡电介质。 在另一个实施例中，蚀刻停止层可以包括邻近柱的阻挡电介质和从阻挡电介质水平延伸到蚀刻停止层中的多个电介质膜。