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    SEMICONDUCTOR DEVICE STRUCTURES FOR BURN-IN TESTING AND METHODS THEREOF
    64.
    发明申请
    SEMICONDUCTOR DEVICE STRUCTURES FOR BURN-IN TESTING AND METHODS THEREOF 审中-公开

    公开(公告)号：US20190170811A1

    公开(公告)日：2019-06-06

    申请号：US16268912

    申请日：2019-02-06

    Applicant: Micron Technology, Inc.

    Inventor： Mark E. Tuttle

    IPC: G01R31/28 ,  H01L23/498 ,  H01L23/00 ,  H01L23/538

    Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate, an electrical connection structure extending upwardly from an upper surface of the substrate by a first height, and a contact pad electrically disposed on the upper surface of the substrate. The contact pad has a solder-wettable surface with an area configured to support a solder ball having a second height at least twice the first height. The semiconductor device structure further includes a fuse element with a first end electrically coupled to the electrical connection structure and a second end electrically coupled to the contact pad.

    Dual sided fan-out package having low warpage across all temperatures
    65.
    发明授权
    Dual sided fan-out package having low warpage across all temperatures 有权

    公开(公告)号：US10304805B2

    公开(公告)日：2019-05-28

    申请号：US15686024

    申请日：2017-08-24

    Applicant: Micron Technology, Inc.

    Inventor： Chan H. Yoo ,  Mark E. Tuttle

    IPC: H01L25/065 ,  H01L25/00

    Abstract: Semiconductor devices including a dual-sided redistribution structure and having low-warpage across all temperatures and associated systems and methods are disclosed herein. In one embodiment, a semiconductor device includes a first semiconductor die electrically coupled to a first side of a redistribution structure and a second semiconductor die electrically coupled to a second side of the redistribution structure opposite the first side. The semiconductor device also includes a first molded material on the first side, a second molded material on the second side, and conductive columns electrically coupled to the first side and extending through the first molded material. The first and second molded materials can have the same volume and/or coefficients of thermal expansion to inhibit warpage of the semiconductor device.

    Stress Tuned Stiffeners for Micro Electronics Package Warpage Control
    66.
    发明申请
    Stress Tuned Stiffeners for Micro Electronics Package Warpage Control 审中-公开

    公开(公告)号：US20190115270A1

    公开(公告)日：2019-04-18

    申请号：US15787321

    申请日：2017-10-18

    Applicant: Micron Technology, Inc.

    Inventor： Chan H. Yoo ,  Mark E. Tuttle

    IPC: H01L23/18 ,  H01L23/373 ,  H01L23/31 ,  H01L21/66

    CPC classification number: H01L23/18 ,  H01L22/12 ,  H01L22/20 ,  H01L23/16 ,  H01L23/3128 ,  H01L23/3135 ,  H01L23/373 ,  H01L23/562

    Abstract: A semiconductor device assembly including a substrate, a semiconductor device, a stiffener member, and mold compound. The stiffener member is tuned, or configured, to reduce and/or control the shape of warpage of the semiconductor device assembly at an elevated temperature. The stiffener member may be placed on the substrate, on the semiconductor device, and/or on the mold compound. A plurality of stiffener members may be used. The stiffener members may be positioned in a predetermined pattern on a component of the semiconductor device assembly. A stiffener member may be used so that the warpage of a first semiconductor device substantially corresponds to the warpage of a second semiconductor device at an elevated temperature. The stiffener member may be tuned by providing the member with a desired coefficient of thermal expansion (CTE). The desired CTE may be based on the individual CTEs of the components of a semiconductor device assembly.

    Thrumold post package with reverse build up hybrid additive structure
    67.
    发明授权
    Thrumold post package with reverse build up hybrid additive structure 有权

    公开(公告)号：US10103038B1

    公开(公告)日：2018-10-16

    申请号：US15685921

    申请日：2017-08-24

    Applicant: Micron Technology, Inc.

    Inventor： Chan H. Yoo ,  John F. Kaeding ,  Ashok Pachamuthu ,  Mark E. Tuttle

    IPC: H01L21/00 ,  H01L21/56 ,  H01L23/31

    Abstract: Semiconductor devices having a semiconductor die electrically coupled to a redistribution structure and a molded material over the redistribution structure are disclosed herein, along with associated systems and methods. In one embodiment, a semiconductor device includes a semiconductor die attached to a first side of a substrate-free redistribution structure, and a plurality of conductive columns extending through a molded material disposed on the first side of the redistribution structure. The semiconductor device can also include a second redistribution structure on the molded material and electrically coupled to the conductive columns. A semiconductor device can be manufactured using a single carrier and requiring processing on only a single side of the semiconductor device.

    SEMICONDUCTOR DEVICE STRUCTURES AND PRINTED CIRCUIT BOARDS COMPRISING SEMICONDUCTOR DEVICES
    68.
    发明申请
    SEMICONDUCTOR DEVICE STRUCTURES AND PRINTED CIRCUIT BOARDS COMPRISING SEMICONDUCTOR DEVICES 有权
    包含半导体器件的半导体器件结构和印刷电路板

    公开(公告)号：US20130228922A1

    公开(公告)日：2013-09-05

    申请号：US13848914

    申请日：2013-03-22

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： Mark E. Tuttle

    IPC: H01L23/538 ,  H05K7/06

    CPC classification number: H01L23/5384 ,  H01L21/76898 ,  H01L23/481 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/0557 ,  H01L2224/13009 ,  H01L2224/13025 ,  H01L2224/131 ,  H01L2224/16146 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/09701 ,  H05K7/06 ,  H01L2924/014 ,  H01L2224/05552

    Abstract: The present invention relates to methods for forming through-wafer interconnects in semiconductor substrates and the resulting structures. In one embodiment, a method for forming a through-wafer interconnect includes providing a substrate having a pad on a surface thereof, depositing a passivation layer over the pad and the surface of the substrate, and forming an aperture through the passivation layer and the pad using a substantially continuous process. An insulative layer is deposited in the aperture followed by a conductive layer and a conductive fill. In another embodiment of the invention, a semiconductor device is formed including a first interconnect structure that extends through a conductive pad and is electrically coupled with the conductive pad while a second interconnect structure is formed through another conductive pad while being electrically isolated therefrom. Semiconductor devices and assemblies produced with the methods are also disclosed.

    Abstract translation: 本发明涉及在半导体衬底中形成贯穿晶片互连的方法以及所得到的结构。 在一个实施例中，用于形成贯通晶片互连的方法包括提供在其表面上具有焊盘的衬底，在焊盘和衬底的表面上沉积钝化层，以及通过钝化层和焊盘形成孔 使用基本上连续的过程。 绝缘层沉积在孔中，随后是导电层和导电填料。 在本发明的另一实施例中，形成半导体器件，其包括延伸穿过导电焊盘并与导电焊盘电耦合的第一互连结构，而第二互连结构通过另一个导电焊盘形成，同时与之电绝缘。 还公开了使用该方法制造的半导体器件和组件。

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