公开(公告)号：US11688467B2

公开(公告)日：2023-06-27

申请号：US17347570

申请日：2021-06-14

Applicant: Micron Technology, Inc.

Inventor： Zhengang Chen ,  Sai Krishna Mylavarapu ,  Zhenlei Shen ,  Tingjun Xie ,  Charles S. Kwong

IPC: G11C16/34 ,  G11C29/52 ,  G06F11/10 ,  G11C16/26 ,  G11C29/42 ,  G06F11/07 ,  G06F11/14 ,  G11C29/44 ,  G11C29/04

CPC classification number: G11C16/3404 ,  G06F11/076 ,  G06F11/1048 ,  G06F11/1068 ,  G06F11/141 ,  G11C16/26 ,  G11C29/42 ,  G11C29/44 ,  G11C29/52 ,  G06F2201/81 ,  G11C2029/0411

Abstract: Described herein are embodiments related to defect detection in memory components of memory systems with time-varying bit error rate. A processing device determines that a bit error rate (BER) corresponding to a read operation to read a unit of data in a memory component satisfies a threshold criterion, determines a write-to-read (W2R) delay for the read operation, wherein the W2R delay comprises a difference between a time of the read operation and a write timestamp indicating when the unit of data was written to the memory component, and determines whether the W2R delay is within a W2R delay range corresponding to an initial read voltage level used by the read operation to read the unit of data. The processing device initiates a defect detection operation responsive to the W2R delay being within the W2R delay range, the defect detection operation to detect time-varying defects in the memory component.

公开(公告)号：US20230195381A1

公开(公告)日：2023-06-22

申请号：US17645683

申请日：2021-12-22

Applicant: Micron Technology, Inc.

Inventor： Tao Liu ,  Zhengang Chen ,  Ting Luo

IPC: G06F3/06 ,  G11C16/26 ,  G11C16/10

CPC classification number: G06F3/0659 ,  G06F3/0611 ,  G06F3/0679 ,  G11C16/26 ,  G11C16/10 ,  G11C16/0483

Abstract: Methods, systems, and devices for a corrective read of a memory device with reduced latency are described. A memory system may identify a read error based on accessing a memory device, and may select a trim setting for a performing a corrective read operation based on a data retention condition associated with the accessed memory device. Such a data retention condition may be associated with a data retention duration, or a cross-temperature condition, among other criteria or combinations thereof. In some implementations, the memory system may select from a subset of possible trim settings, which may be associated with relevant process corners. For example, the memory system may select between a first trim setting that is associated with a relatively large cross-temperature and a relatively short data retention duration and a second trim setting that is associated with a relatively small cross-temperature and a relatively long data retention duration.

公开(公告)号：US11632132B2

公开(公告)日：2023-04-18

申请号：US17447864

申请日：2021-09-16

Applicant: Micron Technology, Inc.

Inventor： Eyal En Gad ,  Zhengang Chen ,  Sivagnanam Parthasarathy ,  Yoav Weinberg

IPC: H03M13/11 ,  H03M13/09 ,  H03M13/29 ,  H03M13/15

Abstract: A processing device in a memory system receives a request to read data from a memory device. In response to receiving the request, the processing device performs an iterative error correction process on the data, wherein at least one iteration after a first iteration in the error correction process uses a criterion that is based at least partially on a previous iteration or partial iteration, and wherein performing the iterative error correction process comprises flipping any bits in the data having an associated number of unsatisfied parity check equations that satisfies a threshold criterion associated with the previous iteration.

公开(公告)号：US11625299B1

公开(公告)日：2023-04-11

申请号：US17645183

申请日：2021-12-20

Applicant: Micron Technology, Inc.

Inventor： Stephen D. Hanna ,  Zhengang Chen

IPC: G06F11/10

Abstract: Methods, systems, and devices for inserting temperature information into a codeword are described. A memory system may determine that a predetermined set of bits of a codeword has been received. Based on determining that the predetermine set of bits has been received, the memory system may replace bits of the codeword with temperature information that indicates a temperature of the memory system. The memory system may then store the codeword comprising the temperature information in a memory array.

公开(公告)号：US20230086696A1

公开(公告)日：2023-03-23

申请号：US17477859

申请日：2021-09-17

Applicant: Micron Technology, Inc.

Inventor： Zhengang Chen ,  Sivagnanam Parthasarathy

IPC: G06F11/10 ,  G06F3/06

Abstract: A plurality of codewords are programmed to one or more memory pages of a memory sub-system. Each memory page of the memory sub-system is associated with a logical unit of a plurality of logical units of the memory sub-system and at least one of a plane of a plurality of planes of the memory sub-system or a block of a plurality of blocks of the memory sub-system. Each codeword of the plurality of codewords comprises host data and base parity bits. A plurality of additional parity bits are programmed to the one or more memory pages of the memory sub-system, wherein each additional parity bit of the plurality of additional parity bits is associated with a codeword of the plurality of standard codewords. A first set of redundancy metadata is generated corresponding to each of the additional parity bits. The first set of redundancy metadata is programmed to a memory page separate from any memory page storing the additional parity bits.

公开(公告)号：US20230015706A1

公开(公告)日：2023-01-19

申请号：US17953269

申请日：2022-09-26

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Tingjun Xie ,  Zhengang Chen ,  Zhenlei Shen

IPC: G06F9/50 ,  G11C11/4074 ,  G06F12/06

Abstract: A system can include a memory component and a processing device. The processing device can receive an indication to remove a group of memory cells of a memory sub-system from a logical address space that is used to access the memory sub-system. The processing device can, responsive to receiving the indication, remove the group of memory cells of the memory sub-system from the logical address space. The processing device can program the group of memory cells that have been removed from the logical address space with a voltage state.

公开(公告)号：US11374592B2

公开(公告)日：2022-06-28

申请号：US16806826

申请日：2020-03-02

Applicant: Micron Technology, Inc.

Inventor： Eyal En Gad ,  Zhengang Chen ,  Sivagnanam Parthasarathy ,  Yoav Weinberg

IPC: H03M13/11 ,  H03M13/15 ,  H03M13/00 ,  G06F11/10

Abstract: A processing device in a memory system reads a sense word from a memory device and executes a plurality of parity check equations on corresponding subsets of the sense word to determine a plurality of parity check equation results. The processing device determines a syndrome for the sense word using the plurality of parity check equation results, determines whether the syndrome for the sense word satisfies a codeword criterion, and responsive to the syndrome for the sense word not satisfying the codeword criterion, performs an iterative low density parity check (LDPC) correction process, wherein at least one criterion of the iterative LDPC correction process is adjusted after a threshold number of iterations is performed.

公开(公告)号：US20220171703A1

公开(公告)日：2022-06-02

申请号：US17676595

申请日：2022-02-21

Applicant: Micron Technology, Inc.

Inventor： Zhengang Chen ,  Jianmin Huang

IPC: G06F12/02 ,  G06F12/0804 ,  G06F12/0817 ,  G06F9/30 ,  G06F11/10 ,  G06F12/14

Abstract: Disclosed in some examples are methods, systems, devices, and machine-readable mediums that provide for techniques for scrambling and/or updating meta-data that enable an efficient internal copyback operation. In some examples, in order to update the meta-data, the meta-data and host-data are separated and the only the meta-data is sent to the controller to be updated during a modified internal copyback operation. The host-data is not transmitted to the controller. While sending the meta-data utilizes resources of the communication link between the memory dies and the controller, it uses much fewer resources than if the host-data were also transmitted.

公开(公告)号：US20210304826A1

公开(公告)日：2021-09-30

申请号：US17347570

申请日：2021-06-14

Applicant: Micron Technology, Inc.

Inventor： Zhengang Chen ,  Sai Krishna Mylavarapu ,  Zhenlei Shen ,  Tingjun Xie ,  Charles S. Kwong

IPC: G11C16/34 ,  G11C29/52 ,  G06F11/10 ,  G11C16/26 ,  G11C29/42 ,  G06F11/07 ,  G06F11/14 ,  G11C29/44

Abstract: Described herein are embodiments related to defect detection in memory components of memory systems with time-varying bit error rate. A processing device determines that a bit error rate (BER) corresponding to a read operation to read a unit of data in a memory component satisfies a threshold criterion, determines a write-to-read (W2R) delay for the read operation, wherein the W2R delay comprises a difference between a time of the read operation and a write timestamp indicating when the unit of data was written to the memory component, and determines whether the W2R delay is within a W2R delay range corresponding to an initial read voltage level used by the read operation to read the unit of data. The processing device initiates a defect detection operation responsive to the W2R delay being within the W2R delay range, the defect detection operation to detect time-varying defects in the memory component.

公开(公告)号：US20210295900A1

公开(公告)日：2021-09-23

申请号：US17339047

申请日：2021-06-04

Applicant: Micron Technology, Inc.

Inventor： Tingjun Xie ,  Seungjune Jeon ,  Zhengang Chen ,  Zhenlei Shen ,  Charles See Yeung Kwong

IPC: G11C11/406 ,  G11C11/16

Abstract: A media management operation can be performed at a memory sub-system at a current frequency. An operating characteristic associated with the memory sub-system can be identified. The operating characteristic can reflect at least one of a write count, a bit error rate, or a read-retry trigger rate. A determination can be made as to whether the identified operating characteristic satisfies an operating characteristic criterion. In response to determining that the operating characteristic satisfies the characteristic criterion, the media management operation can be performed at a different frequency relative to the current frequency.