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85 条记录 (耗时 0.021 秒)

    Semiconductor device
    62.
    发明授权
    Semiconductor device 有权
    半导体器件

    公开(公告)号：US06498522B2

    公开(公告)日：2002-12-24

    申请号：US09833045

    申请日：2001-04-12

    申请人： Hitoshi Ikeda ,  Shinya Fujioka ,  Yasuharu Sato ,  Yasurou Matsuzaki

    发明人： Hitoshi Ikeda ,  Shinya Fujioka ,  Yasuharu Sato ,  Yasurou Matsuzaki

    IPC分类号： H03L700

    CPC分类号： G11C7/1084 ,  G11C7/1072 ,  G11C7/1078 ,  G11C7/1093 ,  G11C7/22 ,  G11C7/222

    摘要： The invention relates to a clock synchronous type semiconductor device that accepts an input signal inputted from the exterior in synchronization with a clock signal. The semiconductor device according to the invention includes an input signal receiving unit that receives an input signal inputted from the exterior, where the receiving is done in synchronization with a clock signal; a clock timing selecting unit for outputting a clock selecting signal; and a clock generating unit that, in response to receiving a clock selecting signal and an external clock signal, generates a clock signal at a predetermined timing which corresponds to a signal level of the clock selecting signal, and outputs the clock signal to the input signal receiving unit, wherein it is possible to securely accept an input signal regardless of the frequency of the external clock signal.

    摘要翻译： 本发明涉及一种时钟同步型半导体器件，其与时钟信号同步地接收从外部输入的输入信号。 根据本发明的半导体器件包括输入信号接收单元，其接收从外部输入的输入信号，其中接收与时钟信号同步完成; 时钟定时选择单元，用于输出时钟选择信号; 以及时钟发生单元，响应于接收到时钟选择信号和外部时钟信号，在与时钟选择信号的信号电平相对应的预定定时产生时钟信号，并将时钟信号输出到输入信号 接收单元，其中无论外部时钟信号的频率如何，都可以安全地接受输入信号。

    Dynamic memory circuit with automatic refresh function
    63.
    发明授权
    Dynamic memory circuit with automatic refresh function 失效
    动态内存电路具有自动刷新功能

    公开(公告)号：US06438055B1

    公开(公告)日：2002-08-20

    申请号：US09688941

    申请日：2000-10-17

    申请人： Masao Taguchi ,  Yasurou Matsuzaki

    发明人： Masao Taguchi ,  Yasurou Matsuzaki

    IPC分类号： G11C700

    CPC分类号： G11C11/406

    摘要： The present invention is that in a dynamic memory circuit, first and second internal operation cycles are assigned to one external operation cycle according to external commands, a memory core performs a read operation which corresponds to a read command at the first internal operation, and performs a refresh operation which responds to a refresh command at the second internal operation cycle. Also the memory core performs a refresh operation which responds to a refresh command at the first internal operation cycle, and performs a write operation which corresponds to a write command at the second internal operation cycle. It is preferable that when the read or write command is not input, the refresh operation is performed at the earlier internal operation cycle. And a refresh command generation circuit which generates the refresh command at a refresh time is created in the memory circuit.

    摘要翻译： 本发明是在动态存储电路中，根据外部指令将第一和第二内部动作周期分配给一个外部动作周期，在第一内部动作中，存储器核心进行与读出命令对应的读取动作， 在第二内部操作周期响应刷新命令的刷新操作。 此外，存储器核心执行在第一内部操作周期响应刷新命令的刷新操作，并且在第二内部操作周期执行与写入命令相对应的写入操作。 优选的是，当没有输入读取或写入命令时，在较早的内部操作周期执行刷新操作。 并且在存储器电路中创建在刷新时间产生刷新命令的刷新命令产生电路。

    Self-timing control circuit
    65.
    发明授权
    Self-timing control circuit 有权
    自定时控制电路

    公开(公告)号：US06239635B1

    公开(公告)日：2001-05-29

    申请号：US09325555

    申请日：1999-06-04

    申请人： Yasurou Matsuzaki

    发明人： Yasurou Matsuzaki

    IPC分类号： H03L700

    CPC分类号： G11C7/1057 ,  G11C7/1051 ,  G11C7/1072 ,  G11C7/222 ,  H03K3/03 ,  H03K3/354 ,  H03K5/13 ,  H03K2005/00247 ,  H03L7/00

    摘要： A self-timing control circuit relating to the present invention comprises a clock cycle counting circuit for counting ocillation pulses during a period corresponding to a cycle of the master clock and generating a clock cycle count value. The count value for a period corresponding to the cycle of the master clock is calculated with this clock cycle counting circuit. The self-timing control circuit further comprises a control clock generating portion for generating the control clock, as timed by synchronizing with the master clock, starting a count of the oscillation pulses, and counting up to the clock cycle count value. As a result, the control clock generated is delayed from the master clock by the time taken to count to the measured count value. The timing of the control clock is delayed from the master clock by one cycle or an integer multiple thereof.

    摘要翻译： 涉及本发明的自定时控制电路包括时钟周期计数电路，用于在对应于主时钟的周期的周期内计数闭合脉冲并产生时钟周期计数值。 通过该时钟周期计数电路计算与主时钟的周期对应的期间的计数值。 自定时控制电路还包括控制时钟产生部分，用于通过与主时钟同步，启动振荡脉冲的计数并计数到时钟周期计数值来产生控制时钟。 结果，产生的控制时钟从主时钟延迟计数到测量的计数值所花费的时间。 控制时钟的定时从主时钟延迟一个周期或其整数倍。

    Memory circuit with automatic precharge function, and integrated circuit device with automatic internal command function
    69.
    发明申请
    Memory circuit with automatic precharge function, and integrated circuit device with automatic internal command function 有权
    具有自动预充功能的记忆电路，具有自动内部指令功能的集成电路器件

    公开(公告)号：US20060187732A1

    公开(公告)日：2006-08-24

    申请号：US11413204

    申请日：2006-04-28

    申请人： Yasurou Matsuzaki

    发明人： Yasurou Matsuzaki

    IPC分类号： G11C7/00

    CPC分类号： G11C11/406 ,  G11C11/40603 ,  G11C11/40615 ,  G11C11/40618 ,  G11C11/4072 ,  G11C11/4094 ,  G11C2211/4061 ,  G11C2211/4065

    摘要： According to the present invention, a memory circuit requiring refresh operations a first circuit which receives a command in synchronization with a clock signal, and which generates a first internal command internally and a second circuit which generates a second internal command, e.g., a refresh command, internally in a prescribed refresh cycle. And an internal circuit, according to said first internal command, executes corresponding control through clock-synchronous operations, and when said refresh command is issued, sequentially executes control corresponding to the refresh command and control corresponding to said first internal command through clock-asynchronous operations. According to the present invention, when a refresh timing signal is generated, the refresh operation can be intrupted among the external command operations.

    摘要翻译： 根据本发明，一种需要刷新操作的存储电路，第一电路接收与时钟信号同步的命令，并且内部产生第一内部命令，第二电路产生第二内部命令，例如刷新命令 在规定的刷新周期内部。 并且根据所述第一内部命令，内部电路通过时钟同步操作执行相应的控制，并且当发出所述刷新命令时，通过时钟异步操作顺序执行对应于刷新命令的控制和对应于所述第一内部命令的控制 。 根据本发明，当产生刷新定时信号时，可以在外部命令操作中中断刷新操作。

    Memory circuit with automatic precharge function, and integrated circuit device with automatic internal command function
    70.
    发明授权
    Memory circuit with automatic precharge function, and integrated circuit device with automatic internal command function 失效
    具有自动预充功能的记忆电路，具有自动内部指令功能的集成电路器件

    公开(公告)号：US07064997B2

    公开(公告)日：2006-06-20

    申请号：US10830149

    申请日：2004-04-23

    申请人： Yasurou Matsuzaki

    发明人： Yasurou Matsuzaki

    IPC分类号： G11C7/00

    CPC分类号： G11C11/406 ,  G11C11/40603 ,  G11C11/40615 ,  G11C11/40618 ,  G11C11/4072 ,  G11C11/4094 ,  G11C2211/4061 ,  G11C2211/4065

    摘要： A memory circuit requiring refresh operations, the memory circuit includes a memory core having memory cells, and a memory control circuit which, for M external operation cycles, where M is greater than or equal to 2, has N internal operation cycles, where N is greater than M and less than 2M. The memory circuit also includes a refresh command generation circuit which generates refresh commands, and wherein the N internal operation cycles includes first internal operation cycles which execute external commands corresponding to the external operation cycles, and second internal operation cycles which execute the refresh commands, and the refresh command generation circuit generates the refresh commands according to a reception of the external command.

    摘要翻译： 一种需要刷新操作的存储器电路，该存储电路包括一个具有存储单元的存储器芯，以及一个存储器控制电路，对于M个大于或等于2的M个外部操作周期，具有N个内部操作周期，其中N是 大于M且小于2M。 存储电路还包括产生刷新命令的刷新命令产生电路，其中N个内部操作周期包括执行与外部操作周期相对应的外部命令的第一内部操作周期和执行刷新命令的第二内部操作周期，以及 刷新命令生成电路根据外部命令的接收生成刷新命令。