公开(公告)号：US5107459A

公开(公告)日：1992-04-21

申请号：US513315

申请日：1990-04-20

申请人： Christopher M. Chu ,  Sang H. Dhong ,  Wei Hwang ,  Nicky C-C. Lu

发明人： Christopher M. Chu ,  Sang H. Dhong ,  Wei Hwang ,  Nicky C-C. Lu

IPC分类号： H01L27/10 ,  G11C11/401 ,  G11C11/4097 ,  H01L21/8242 ,  H01L27/108

CPC分类号： H01L27/10841 ,  G11C11/4097

摘要： A stacked bit-line architecture utilizing high density cross-point memory arrays forms a DRAM semiconductor memory device. The true and complementary bit-line pairs connected to the respective memory cell arrays are formed in two metal layers, one above the other. A bit-line interconnector region is provided that uses a third interconnection layer together with the first and second layers to transpose the vertical stacking of each pair and to transpose the planar alignment of adjacent bit-line pairs. The DRAM memory cell array has a high density cross-point memory cell architecture that behaves electrically as a folded bit-line array.

公开(公告)号：US4881105A

公开(公告)日：1989-11-14

申请号：US206148

申请日：1988-06-13

申请人： Bijan Davari ,  Wei Hwang ,  Nicky C. Lu

发明人： Bijan Davari ,  Wei Hwang ,  Nicky C. Lu

IPC分类号： H01L21/336 ,  H01L21/8238 ,  H01L27/04 ,  H01L27/092 ,  H01L29/423 ,  H01L29/78

CPC分类号： H01L29/7827 ,  H01L21/823885 ,  H01L27/0925 ,  H01L29/66666 ,  H01L29/4236

摘要： An integrated, self-aligned trench-transistor structure including trench CMOS devices and vertical "strapping transistors" wherein the shallow trench transistors and the strapping trench-transistors are built on top of buried source junctions. A p- epitaxial layer is grown on a substrate and contains an n-well, an n+ source and a p+ source regions. Shallow trenches are disposed in the epitaxial layer and contain n+ polysilicon or metal, such as tungsten, to provide the trench CMOS gates. A gate contact region connects the trenches and the n+ polysilicon or metal in the trenches. The n+ polysilicon or metal in the trenches are isolated by a thin layer of silicon dioxide on the trench walls of the gates. The p+ drain region, along with the filled trench gate element and the p+ source region, form a vertical p-channel (PMOS) trench-transistor. The n+ drain region, along with filled trench gate element and the n+ source form a vertical n-channel (NMOS) transistor. The PMOS and NMOS trench transistors are isolated by shallow trench isolation regions and an oxide layer.

公开(公告)号：US4763180A

公开(公告)日：1988-08-09

申请号：US945275

申请日：1986-12-22

申请人： Wei Hwang ,  Stanley E. Schuster ,  Lewis M. Terman

发明人： Wei Hwang ,  Stanley E. Schuster ,  Lewis M. Terman

IPC分类号： G11C11/401 ,  H01L21/74 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/04 ,  H01L27/10 ,  H01L27/108 ,  G11C11/40

CPC分类号： H01L21/743 ,  H01L21/8221 ,  H01L27/10841

摘要： A vertical DRAM cell using VMOS transistors and trench capacitors and the fabrication process therefor. A vertical DRAM structure comprising a VMOS transistor and trench capacitor in combination is provided wherein the access transistors are in a V-groove and the capacitors are in two vertical layers. The structure has only a single level of polysilicon and has no contacts. The memory cell circuit is a one-device memory cell, having a single access transistor with its gate connected to a word line, its drain connected to a bit line, and its source connected to a storage capacitor. More particularly, the storage capacitance node is connected to the source of the V-groove access device through a conducting bridge. The gate of the V-groove access device is connected to the polysilicon word line and the drain is a diffused region which also serves as the bit line of the cell. An epitaxial layer is grown over a combination of single crystalline material and oxide. Polycrystalline regions in the silicon substrate have an oxide covering. In an alternate version, a single crystal epitaxial layer is disposed over regions consisting of both single crystal and poly crystal Si or polycrystalline material on top of single crystalline material is converted into single crystalline material.

公开(公告)号：US4532698A

公开(公告)日：1985-08-06

申请号：US623810

申请日：1984-06-22

申请人： Frank F. Fang ,  Bertrand M. Grossman ,  Wei Hwang

发明人： Frank F. Fang ,  Bertrand M. Grossman ,  Wei Hwang

IPC分类号： H01L29/78 ,  H01L21/033 ,  H01L21/265 ,  H01L21/28 ,  H01L21/336 ,  H01L29/423 ,  H01L21/283 ,  H01L21/22

CPC分类号： H01L29/66659 ,  H01L21/0337 ,  H01L21/26586 ,  H01L21/2815 ,  H01L29/42376 ,  H01L29/66545 ,  Y10S148/082

摘要： The combined use of an angularly deposited mask with a subsequent angular conductivity conversion operation extending partially under the mask permits both shorter dimensions and the ability to accommodate the straggle location change when subsequent processing steps occur. The mask is deposited at a low angle with respect to a planar surface, a subsequent conductivity conversion, such as ion implantation, extends under the mask, the mask is removed and a smaller gate is positioned in its location, the gate being smaller than the distance from the source to the point where the conversion extended under the mask, providing thereby an ultra-short gate FET.

摘要翻译： 使用角度沉积的掩模与部分地在掩模下面延伸的随后的角度电导率转换操作的组合使用允许更短的尺寸和当后续处理步骤发生时适应分段位置变化的能力。 掩模以相对于平面表面的低角度沉积，随后的电导率转换（例如离子注入）在掩模下方延伸，掩模被移除，并且较小的栅极位于其位置，栅极小于 从源极到在掩模下延伸的转换点，从而提供超短栅极FET。

公开(公告)号：US20130223136A1

公开(公告)日：2013-08-29

申请号：US13484497

申请日：2012-05-31

申请人： Ching-Te CHUANG ,  Shyh-Jye Jou ,  Wei Hwang ,  Yi-Wei Lin ,  Ming-Chien Tsai ,  Hao-I Yang ,  Ming-Hsien Tu ,  Wei-Chiang Shih ,  Nan-Chun Lien ,  Kuen-Di Lee

发明人： Ching-Te CHUANG ,  Shyh-Jye Jou ,  Wei Hwang ,  Yi-Wei Lin ,  Ming-Chien Tsai ,  Hao-I Yang ,  Ming-Hsien Tu ,  Wei-Chiang Shih ,  Nan-Chun Lien ,  Kuen-Di Lee

IPC分类号： G11C11/40

CPC分类号： G11C29/50 ,  G11C11/41 ,  G11C2029/5002

摘要： The present invention provides a 6T SRAM including a first inverter, a second inverter, a first pass-gate transistor, and a second pass-gate transistor. The first inverter zs a first pull-up transistor and a first pull-down transistor. The second inverter includes a second pull-up transistor and a second pull-down transistor. The gate of the second pull-up transistor is coupled with the gate of the second pull-down transistor, and the drain of the second pull-up transistor is coupled with the drain of the second pull-down transistor. The SRAM can measure the trip voltage, the read disturb voltage, and the write margin by controlling the first bit line, the second bit line, the GND, the first word line, and the voltage source without changing of the physic parameter of the SRAM.

摘要翻译： 本发明提供一种包括第一反相器，第二反相器，第一通过栅极晶体管和第二通过栅极晶体管的6T SRAM。 第一反相器zs是第一上拉晶体管和第一下拉晶体管。 第二反相器包括第二上拉晶体管和第二下拉晶体管。 第二上拉晶体管的栅极与第二下拉晶体管的栅极耦合，并且第二上拉晶体管的漏极与第二下拉晶体管的漏极耦合。 SRAM可以通过控制第一位线，第二位线，GND，第一字线和电压源来测量跳闸电压，读取干扰电压和写入裕度，而不改变SRAM的物理参数 。

公开(公告)号：US08437178B2

公开(公告)日：2013-05-07

申请号：US13096796

申请日：2011-04-28

申请人： Yi-Te Chiu ,  Ming-Hung Chang ,  Hao-I Yang ,  Wei Hwang

发明人： Yi-Te Chiu ,  Ming-Hung Chang ,  Hao-I Yang ,  Wei Hwang

IPC分类号： G11C11/00

CPC分类号： G11C11/412

摘要： A static random access memory cell includes a latch unit. The latch unit includes a bi-inverting circuit and a switching circuit. The bi-inverting circuit has a first terminal and a second terminal. The switching circuit is electrically connected between the first terminal and the second terminal, wherein when the switching circuit is turned on, the switching circuit forms a feedback between the first terminal and the second terminal for latching the latch unit; and when the switching circuit is turned off, the feedback is removed to cause the SRAM cell to write a data bit to the latch unit.

摘要翻译： 静态随机存取存储单元包括一个锁存单元。 锁存单元包括双向电路和开关电路。 双向电路具有第一端子和第二端子。 开关电路电连接在第一端子和第二端子之间，其中当开关电路导通时，开关电路在第一端子和第二端子之间形成用于锁存闩锁单元的反馈; 并且当切换电路关闭时，消除反馈以使SRAM单元向锁存单元写入数据位。

公开(公告)号：US08258741B2

公开(公告)日：2012-09-04

申请号：US12832079

申请日：2010-07-08

申请人： Chun-Yi Wu ,  Wei-Chih Hsieh ,  Wei Hwang

发明人： Chun-Yi Wu ,  Wei-Chih Hsieh ,  Wei Hwang

IPC分类号： H01M10/46

CPC分类号： H02J7/35 ,  H02M3/07 ,  Y02E10/566 ,  Y02E10/58 ,  Y10T307/707

摘要： A solar power management system is provided for managing electric energy conversion by a photovoltaic cell module, supplying the converted electric energy to an external load, and storing the converted electric energy in a battery. The solar power management system comprises a multiphase maximum power tracking (MPT) module, a charging circuit, and a voltage conversion module. The multiphase MPT module regulates output current of the photovoltaic cell module to output maximum power within the high limit thereof and obtain improved solar energy conversion efficiency. The voltage conversion module converts the electric energy generated by the photovoltaic cell module into different voltage formats, such as 5.6V DC, 1.0V DC, 0.6˜0.3V DC low voltage, or −1.2V DC negative voltage, to meet different external load requirements. The solar power management system has simple circuitry and can be configured as a system on chip (SoC) at reduced cost while provides very wide applications.

摘要翻译： 提供了一种太阳能发电管理系统，用于通过光伏电池模块管理电能转换，将转换的电能提供给外部负载，并将转换的电能存储在电池中。 太阳能发电管理系统包括多相最大功率跟踪（MPT）模块，充电电路和电压转换模块。 多相MPT模块调节光伏电池模块的输出电流，以在其上限内输出最大功率，并获得改进的太阳能转换效率。 电压转换模块将光伏电池模块产生的电能转换成不同的电压格式，如5.6V DC，1.0V DC，0.6〜0.3V直流低电压或-1.2V直流负电压，以满足不同的外部负载 要求。 太阳能发电管理系统具有简单的电路，可以以低成本配置为片上系统（SoC），同时提供非常广泛的应用。

公开(公告)号：US20120170616A1

公开(公告)日：2012-07-05

申请号：US13117487

申请日：2011-05-27

申请人： Kun-Ju Tsai ,  Shang-Yuan Lin ,  Shi-Wen Chen ,  Ming-Hung Chang ,  Wei Hwang

发明人： Kun-Ju Tsai ,  Shang-Yuan Lin ,  Shi-Wen Chen ,  Ming-Hung Chang ,  Wei Hwang

IPC分类号： G01K7/00

CPC分类号： G01K7/32 ,  G01K7/01

摘要： An apparatus and a method for sensing temperature are provided. The apparatus includes a first oscillation circuit, a pulse width generator, and a comparison circuit. The first oscillation circuit is for generating a first signal having a first frequency which is related to a to-be-sensed temperature. The pulse width generator is for generating a pulse width signal, the pulse width signal having a pulse width related to the to-be-sensed temperature. The comparison circuit is for generating an output signal indicative of the value of the to-be-sensed temperature according to the first signal and the pulse width signal.

摘要翻译： 提供了一种用于感测温度的装置和方法。 该装置包括第一振荡电路，脉冲宽度发生器和比较电路。 第一振荡电路用于产生具有与待检测温度相关的第一频率的第一信号。 脉冲宽度发生器用于产生脉冲宽度信号，该脉冲宽度信号具有与待感测温度相关的脉冲宽度。 比较电路用于根据第一信号和脉冲宽度信号产生指示待检测温度的值的输出信号。

公开(公告)号：US20120087196A1

公开(公告)日：2012-04-12

申请号：US13075682

申请日：2011-03-30

申请人： Hao-I YANG ,  Ching-Te Chuang ,  Wei Hwang

发明人： Hao-I YANG ,  Ching-Te Chuang ,  Wei Hwang

IPC分类号： G11C5/14

CPC分类号： G11C11/417

摘要： The present invention proposes a gate oxide breakdown-withstanding power switch structure, which is connected with an SRAM and comprises a first CMOS switch and a second CMOS switch respectively having different gate-oxide thicknesses or different threshold voltages. The CMOS switch, which has a normal gate-oxide thickness or a normal threshold voltage, provides current for the SRAM to wake up the SRAM from a standby or sleep mode to an active mode. The CMOS switch, which has a thicker gate-oxide thickness or a higher threshold voltage, provides current for the SRAM to work in an active mode. The present invention prevents a power switch from gate-oxide breakdown lest noise margin, stabilization and performance of SRAM be affected.

摘要翻译： 本发明提出一种栅极氧化物击穿电源开关结构，其与SRAM连接，并且包括分别具有不同栅极氧化物厚度或不同阈值电压的第一CMOS开关和第二CMOS开关。 具有正常栅极氧化物厚度或正常阈值电压的CMOS开关为SRAM提供电流，以将SRAM从待机或睡眠模式唤醒至活动模式。 具有更厚栅极氧化物厚度或更高阈值电压的CMOS开关为SRAM提供工作在主动模式的电流。 本发明防止电源开关从栅极氧化层击穿，以免噪声容限，SRAM的稳定性和性能受到影响。

公开(公告)号：US20110128796A1

公开(公告)日：2011-06-02

申请号：US12772238

申请日：2010-05-03

申请人： Ching-Te Chuang ,  Hao-I Yang ,  Jihi-Yu Lin ,  Shyh-Chyi Yang ,  Ming-Hsien Tu ,  Wei Hwang ,  Shyh-Jye Jou ,  Kun-Ti Lee ,  Hung-Yu Li

发明人： Ching-Te Chuang ,  Hao-I Yang ,  Jihi-Yu Lin ,  Shyh-Chyi Yang ,  Ming-Hsien Tu ,  Wei Hwang ,  Shyh-Jye Jou ,  Kun-Ti Lee ,  Hung-Yu Li

IPC分类号： G11C7/10 ,  G11C7/00

CPC分类号： G11C11/412

摘要： A disturb-free static random access memory cell includes: a latch circuit having a first access terminal and a second access terminal; a first switching circuit having a first bit transferring terminal coupled to the first access terminal, a first control terminal coupled to a first write word line, and a second bit transferring terminal; a second switching circuit having a third bit transferring terminal coupled to the second access terminal, a second control terminal coupled to a second write word line, and a fourth bit transferring terminal coupled to the second bit transferring terminal; a third switching circuit having a fifth bit transferring terminal coupled to the fourth bit transferring terminal, a third control terminal coupled to a word line, and a sixth bit transferring terminal coupled to a bit line; and a sensing amplifier coupled to the bit line, for determining a bit value appearing at the bit line.

摘要翻译： 无干扰的静态随机存取存储单元包括：具有第一接入终端和第二接入终端的锁存电路; 第一切换电路，具有耦合到第一接入终端的第一比特传送终端，耦合到第一写字线的第一控制终端和第二比特传送终端; 第二切换电路，具有耦合到第二接入终端的第三比特传送终端，耦合到第二写字线的第二控制终端，以及耦合到第二比特传送终端的第四比特传送终端。 第三开关电路，具有耦合到第四位转移终端的第五位转移终端，耦合到字线的第三控制端和耦合到位线的第六位转移端; 以及耦合到位线的感测放大器，用于确定出现在位线处的位值。