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公开(公告)号:US20180285374A1
公开(公告)日:2018-10-04
申请号:US15477027
申请日:2017-04-01
申请人: Altug Koker , Prasoonkumar Surti , David Puffer , Subramaniam Maiyuran , Guei-Yuan Lueh , Abhishek R. Appu , Joydeep Ray , Balaji Vembu , Tomer Bar-On , Andrew T. Lauritzen , Hugues Labbe , John G. Gierach , Gabor Liktor
发明人: Altug Koker , Prasoonkumar Surti , David Puffer , Subramaniam Maiyuran , Guei-Yuan Lueh , Abhishek R. Appu , Joydeep Ray , Balaji Vembu , Tomer Bar-On , Andrew T. Lauritzen , Hugues Labbe , John G. Gierach , Gabor Liktor
摘要: In an example, an apparatus comprises a plurality of execution units, and a first memory communicatively couple to the plurality of execution units, wherein the first shared memory is shared by the plurality of execution units and a copy engine to copy context state data from at least a first of the plurality of execution units to the first shared memory. Other embodiments are also disclosed and claimed.
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公开(公告)号:US20180285191A1
公开(公告)日:2018-10-04
申请号:US15477050
申请日:2017-04-01
申请人: Sanjeev S. Jahagirdar , Eric J. Asperheim , Subramaniam Maiyuran , Kiran C. Veernapu , Eric C. Samson , Joydeep Ray , Travis T. Schluessler , Jacek Kwiatkowski , Abhishek R. Appu , Ankur N. Shah , Altug Koker
发明人: Sanjeev S. Jahagirdar , Eric J. Asperheim , Subramaniam Maiyuran , Kiran C. Veernapu , Eric C. Samson , Joydeep Ray , Travis T. Schluessler , Jacek Kwiatkowski , Abhishek R. Appu , Ankur N. Shah , Altug Koker
IPC分类号: G06F11/07
摘要: Methods and apparatus relating to techniques for reference voltage control based on error detection are described. In an embodiment, modification to a reference voltage (to be supplied to one or more components of a processor) is based at least in part on error detection to be detected for a reference circuit. In another embodiment, modification is made to a power characteristic of a processor in response to a determination that the processor is to execute a safety critical application. The modification may include adjustment to an operating frequency and/or an operating voltage of the processor. Other embodiments are also disclosed and claimed.
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公开(公告)号:US20180285158A1
公开(公告)日:2018-10-04
申请号:US15477026
申请日:2017-04-01
申请人: Abhishek R. Appu , Altug Koker , Balaji Vembu , Joydeep Ray , Kamal Sinha , Prasoonkumar Surti , Kiran C. Veernapu , Subramaniam Maiyuran , Sanjeev S. Jahagirdar , Eric J. Asperheim , Guei-Yuan Lueh , David Puffer , Wenyin Fu , Nikos Kaburlasos , Bhushan M. Borole , Josh B. Mastronarde , Linda L. Hurd , Travis T. Schluessler , Tomasz Janczak , Abhishek Venkatesh , Kai Xiao , Slawomir Grajewski
发明人: Abhishek R. Appu , Altug Koker , Balaji Vembu , Joydeep Ray , Kamal Sinha , Prasoonkumar Surti , Kiran C. Veernapu , Subramaniam Maiyuran , Sanjeev S. Jahagirdar , Eric J. Asperheim , Guei-Yuan Lueh , David Puffer , Wenyin Fu , Nikos Kaburlasos , Bhushan M. Borole , Josh B. Mastronarde , Linda L. Hurd , Travis T. Schluessler , Tomasz Janczak , Abhishek Venkatesh , Kai Xiao , Slawomir Grajewski
摘要: In an example, an apparatus comprises a plurality of execution units comprising at least a first type of execution unit and a second type of execution unit and logic, at least partially including hardware logic, to analyze a workload and assign the workload to one of the first type of execution unit or the second type of execution unit. Other embodiments are also disclosed and claimed.
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公开(公告)号:US09336008B2
公开(公告)日:2016-05-10
申请号:US13338887
申请日:2011-12-28
CPC分类号: G06F9/3877 , G06F7/544 , G06F9/3001 , G06F9/30036
摘要: Various embodiments may be disclosed that may share a ROM pull down logic circuit among multiple ports of a processing core. The processing core may include an execution unit (EU) having an array of read only memory (ROM) pull down logic storing math functions. The ROM pull down logic circuit may implement single instruction, multiple data (SIMD) operations. The ROM pull down logic circuit may be operatively coupled with each of the multiple ports in a multi-port function sharing arrangement. Sharing the ROM pull down logic circuit reduces the need to duplicate logic and may result in a savings of chip area as well as a savings of power.
摘要翻译: 可以公开可以在处理核心的多个端口中共享ROM下拉逻辑电路的各种实施例。 处理核心可以包括具有存储数学函数的只读存储器(ROM)下拉逻辑阵列的执行单元(EU)。 ROM下拉逻辑电路可以实现单指令,多数据(SIMD)操作。 ROM下拉逻辑电路可以在多端口功能共享装置中与多个端口中的每一个可操作地耦合。 共享ROM下拉逻辑电路减少了重复逻辑的需要,并且可以节省芯片面积以及节省功率。
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公开(公告)号:US09183014B2
公开(公告)日:2015-11-10
申请号:US13028574
申请日:2011-02-16
CPC分类号: G06F9/547 , G06F9/30061 , G06F9/449 , G06F9/455 , G06F15/8007
摘要: Systems and methods of enabling virtual calls in a single instruction multiple data (SIMD) environment may involve detecting a virtual call of a function and using a single dispatch of the function to invoke the virtual call for two or more channels of the virtual call. In one example, it is determined that the two or more channels share a common target address and a single dispatch of the function is conducted with respect to the common target address. The process may be iterated for additional channels of the virtual call that share a common target address.
摘要翻译: 在单个指令多数据(SIMD)环境中启用虚拟呼叫的系统和方法可以涉及检测功能的虚拟呼叫,并且使用该功能的单个调度来调用虚拟呼叫的两个或多个信道的虚拟呼叫。 在一个示例中,确定两个或更多个信道共享公共目标地址,并且相对于公共目标地址进行该功能的单个调度。 可以对共享共同目标地址的虚拟呼叫的附加信道重复该过程。
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公开(公告)号:US20150046736A1
公开(公告)日:2015-02-12
申请号:US14195737
申请日:2014-03-03
申请人: Deep Buch , Vivek Garg , Subramaniam Maiyuran
发明人: Deep Buch , Vivek Garg , Subramaniam Maiyuran
CPC分类号: G06F1/206 , G06F1/3287
摘要: A method is described that involves controlling the traffic levels through an uncore to provide thermal management for the uncore. The method including determining if an uncore's temperature in a first uncore state is above a first threshold value and changing the first uncore state to a second uncore state if the uncore temperature is above the first threshold value.
摘要翻译: 描述了一种方法,其涉及通过一个无孔部来控制交通等级,以提供对该无孔的热管理。 所述方法包括确定第一非核状态中的非空气温度是否高于第一阈值,并且如果所述非空温度高于所述第一阈值,则将所述第一非空状态改变为第二非空状态。
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公开(公告)号:US20130073834A1
公开(公告)日:2013-03-21
申请号:US13619832
申请日:2012-09-14
IPC分类号: G06F9/312
CPC分类号: G06F9/3836 , G06F9/30043 , G06F9/30047 , G06F9/30087 , G06F9/3012 , G06F9/30145 , G06F9/3808 , G06F9/3812 , G06F9/3834 , G06F9/3855 , G06F9/3857 , G06F9/3867 , G06F2009/45583 , G06F2009/45591
摘要: A system and method for fencing memory accesses. Memory loads can be fenced, or all memory access can be fenced. The system receives a fencing instruction that separates memory access instructions into older accesses and newer accesses. A buffer within the memory ordering unit is allocated to the instruction. The access instructions newer than the fencing instruction are stalled. The older access instructions are gradually retired. When all older memory accesses are retired, the fencing instruction is dispatched from the buffer.
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公开(公告)号:US20120210098A1
公开(公告)日:2012-08-16
申请号:US13028574
申请日:2011-02-16
IPC分类号: G06F9/38
CPC分类号: G06F9/547 , G06F9/30061 , G06F9/449 , G06F9/455 , G06F15/8007
摘要: Systems and methods of enabling virtual calls in a single instruction multiple data (SIMD) environment may involve detecting a virtual call of a function and using a single dispatch of the function to invoke the virtual call for two or more channels of the virtual call. In one example, it is determined that the two or more channels share a common target address and a single dispatch of the function is conducted with respect to the common target address. The process may be iterated for additional channels of the virtual call that share a common target address.
摘要翻译: 在单个指令多数据(SIMD)环境中启用虚拟呼叫的系统和方法可以涉及检测功能的虚拟呼叫,并且使用该功能的单个调度来调用虚拟呼叫的两个或多个信道的虚拟呼叫。 在一个示例中,确定两个或更多个信道共享公共目标地址,并且相对于公共目标地址进行该功能的单个调度。 可以对共享共同目标地址的虚拟呼叫的附加信道重复该过程。
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公开(公告)号:US20110078485A1
公开(公告)日:2011-03-31
申请号:US12570137
申请日:2009-09-30
IPC分类号: G06F1/04
CPC分类号: G11C7/1051 , G11C7/1057 , G11C7/106 , G11C7/1066
摘要: The amount of data that may be transferred between a processing unit and a memory may be increased by transferring information during both the high and low phases of a clock. As one example, in a graphics processor using a general purpose register file as a memory and a mathematical box as a processing unit, the amount of data that can be transferred can be increased by transferring data during both the high and low phases of a clock.
摘要翻译: 可以通过在时钟的高阶段和低阶段之间传送信息来增加可在处理单元和存储器之间传送的数据量。 作为一个例子,在使用通用寄存器文件作为存储器和数学框作为处理单元的图形处理器中,可以通过在时钟的高阶段和低阶段之间传送数据来增加可以传送的数据量 。
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公开(公告)号:US20100262855A1
公开(公告)日:2010-10-14
申请号:US12755339
申请日:2010-04-06
申请人: Deep Buch , Vivek Garg , Subramaniam Maiyuran
发明人: Deep Buch , Vivek Garg , Subramaniam Maiyuran
CPC分类号: G06F1/206 , G06F1/3287
摘要: A method is described that involves controlling the traffic levels through an uncore to provide thermal management for the uncore. The method including determining if an uncore's temperature in a first uncore state is above a first threshold value and changing the first uncore state to a second uncore state if the uncore temperature is above the first threshold value.
摘要翻译: 描述了一种方法,其涉及通过一个无孔部来控制交通等级,以提供对该无孔的热管理。 所述方法包括确定第一非核状态中的非空气温度是否高于第一阈值,并且如果所述非空温度高于所述第一阈值,则将所述第一非空状态改变为第二非空状态。
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