公开(公告)号：US20180091705A1

公开(公告)日：2018-03-29

申请号：US15714483

申请日：2017-09-25

Applicant: Rambus Inc.

Inventor： Patrick R. Gill ,  Thomas Vogelsang

IPC: H04N5/217

CPC classification number: H04N5/2173 ,  G02B5/1842 ,  G02B27/0056 ,  G02B27/0068 ,  G02B27/4205

Abstract: An imaging system with a diffractive optic captures an interference pattern responsive to light from an imaged scene to represent the scene in a spatial-frequency domain. The sampled frequency-domain image data has properties that are determined by the point-spread function of diffractive optic and characteristics of scene. An integrated processor can modified the sampled frequency-domain image data responsive to such properties before transforming the modified frequently-domain image data into the pixel domain.

公开(公告)号：US20170256290A1

公开(公告)日：2017-09-07

申请号：US15603333

申请日：2017-05-23

Applicant: Rambus Inc.

Inventor： Thomas Vogelsang

IPC: G11C5/06 ,  H01L23/48 ,  H01L27/108 ,  H01L25/065 ,  G11C5/02

CPC classification number: G11C5/063 ,  G11C5/025 ,  H01L23/481 ,  H01L25/0657 ,  H01L27/10897 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06596 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A memory device includes a first dynamic random access memory (DRAM) integrated circuit (IC) chip including first memory core circuitry, and first input/output (I/O) circuitry. A second DRAM IC chip is stacked vertically with the first DRAM IC chip. The second DRAM IC chip includes second memory core circuitry, and second I/O circuitry. Solely one of the first DRAM IC chip or the second DRAM IC chip includes a conductive path that electrically couples at least one of the first memory core circuitry or the second memory core circuitry to solely one of the first I/O circuitry or the second I/O circuitry, respectively.

公开(公告)号：US09570144B2

公开(公告)日：2017-02-14

申请号：US15046820

申请日：2016-02-18

Applicant: Rambus Inc.

Inventor： Richard Perego ,  Thomas Vogelsang ,  John Brooks

IPC: G11C11/406 ,  G11C11/408

CPC classification number: G11C11/406 ,  G11C11/40603 ,  G11C11/40611 ,  G11C11/40618 ,  G11C11/408 ,  G11C2211/4061

Abstract: The present disclosure describes DRAM architectures and refresh controllers that allow for scheduling of an opportunistic refresh of a DRAM device concurrently with normal row activate command directed toward the DRAM device. Each activate command affords an “opportunity” to refresh another independent row (i.e., a wordline) within a memory device with no scheduling conflict.

Abstract translation: 本公开描述了DRAM架构和刷新控制器，其允许与指向DRAM设备的正常行激活命令同时调度DRAM设备的机会性刷新。 每个激活命令提供了在没有调度冲突的情况下刷新存储器设备内的另一独立行（即字线）的“机会”。

公开(公告)号：US09515008B2

公开(公告)日：2016-12-06

申请号：US15019867

申请日：2016-02-09

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  Ely Tsern ,  Thomas Vogelsang

IPC: H01L23/538 ,  H01L23/48 ,  H01L25/065 ,  H01L25/18 ,  G06F3/06

CPC classification number: H01L23/481 ,  G06F3/0604 ,  G06F3/0629 ,  G06F3/0673 ,  G06F2213/0038 ,  H01L25/0657 ,  H01L25/18 ,  H01L2224/131 ,  H01L2224/16146 ,  H01L2225/06544 ,  H01L2924/014

Abstract: An integrated circuit die includes conductive connection sites located at least on a surface of the integrated circuit die within a contiguous region thereof. The integrated circuit also includes a core circuit located outside the contiguous region. The core circuit is coupled to at least one of the connection sites.

公开(公告)号：US09437280B2

公开(公告)日：2016-09-06

申请号：US14506507

申请日：2014-10-03

Applicant: Rambus Inc.

Inventor： Thomas Vogelsang ,  Gary B. Bronner

IPC: G11C7/00 ,  G11C11/4091 ,  G11C7/06 ,  G11C7/08 ,  G11C11/4094 ,  G11C11/4096 ,  H01L27/108

CPC classification number: G11C11/4091 ,  G11C7/065 ,  G11C7/08 ,  G11C11/4094 ,  G11C11/4096 ,  H01L27/10873 ,  H01L27/10897

Abstract: The disclosed embodiments provide a sense amplifier for a dynamic random-access memory (DRAM). This sense amplifier includes a bit line to be coupled to a cell to be sensed in the DRAM, and a complement bit line which carries a complement of a signal on the bit line. The sense amplifier also includes a p-type field-effect transistor (PFET) pair comprising cross-coupled PFETs that selectively couple either the bit line or the complement bit line to a high bit-line voltage. The sense amplifier additionally includes an n-type field effect transistor (NFET) pair comprising cross-coupled NFETs that selectively couple either the bit line or the complement bit line to ground. This NFET pair is lightly doped to provide a low threshold-voltage mismatch between NFETs in the NFET pair. In one variation, the gate material for the NFETs is selected to have a work function that compensates for a negative threshold voltage in the NFETs which results from the light substrate doping. In another variation, the sense amplifier additionally includes a cross-coupled pair of latching NFETs. These latching NFETs are normally doped and are configured to latch the voltage on the bit line after the lightly doped NFETs finish sensing the voltage on the bit line.

Abstract translation: 所公开的实施例提供用于动态随机存取存储器（DRAM）的读出放大器。 该读出放大器包括要耦合到要在DRAM中感测的单元的位线以及在位线上承载信号的补码的补码位线。 读出放大器还包括p型场效应晶体管（PFET）对，其包括选择性地将位线或补码位线耦合到高位线电压的交叉耦合PFET。 读出放大器另外包括n型场效应晶体管（NFET）对，其包括交叉耦合NFET，其选择性地将位线或补码位线耦合到地。 该NFET对被轻掺杂以在NFET对中的NFET之间提供低阈值电压失配。 在一个实施例中，用于NFET的栅极材料被选择为具有补偿由于衬底掺杂导致的NFET中的负阈值电压的功函数。 在另一变型中，读出放大器另外包括交叉耦合的一对锁存NFET。 这些锁存NFET通常是掺杂的，并且被配置为在轻掺杂NFET完成感测位线上的电压之后锁存位线上的电压。

公开(公告)号：US09264639B2

公开(公告)日：2016-02-16

申请号：US14616546

申请日：2015-02-06

Applicant: Rambus Inc.

Inventor： Michael Guidash ,  Jay Endsley ,  John Ladd ,  Thomas Vogelsang ,  Craig M. Smith

IPC: H04N5/374 ,  H04N5/365 ,  H04N5/378 ,  H04N5/376 ,  H04N5/357 ,  H01L27/146

CPC classification number: H04N5/374 ,  H01L27/14643 ,  H04N5/3577 ,  H04N5/365 ,  H04N5/3765 ,  H04N5/378

Abstract: A control pulse is generated a first control signal line coupled to a transfer gate of a pixel to enable photocharge accumulated within a photosensitive element of the pixel to be transferred to a floating diffusion node, the first control signal line having a capacitive coupling to the floating diffusion node. A feedthrough compensation pulse is generated on a second signal line of the pixel array that also has a capacitive coupling to the floating diffusion node. The feedthrough compensation pulse is generated with a pulse polarity opposite the pulse polarity of the control pulse and is timed to coincide with the control pulse such that capacitive feedthrough of the control pulse to the floating diffusion node is reduced.

Abstract translation: 生成控制脉冲，该第一控制信号线耦合到像素的传输门，以使得能够累积在该像素的光敏元件内的光电荷被传送到浮动扩散节点，该第一控制信号线具有与浮置的电容耦合 扩散节点。 在像素阵列的还具有与浮动扩散节点的电容耦合的第二信号线上产生馈通补偿脉冲。 馈通补偿脉冲以与控制脉冲的脉冲极性相反的脉冲极性产生，并被定时以与控制脉冲一致，使得控制脉冲到浮动扩散节点的电容馈通减小。

公开(公告)号：US09256376B2

公开(公告)日：2016-02-09

申请号：US14452373

申请日：2014-08-05

Applicant: Rambus Inc.

Inventor： Ely Tsern ,  Thomas Vogelsang ,  Craig Hampel ,  Scott C. Best

IPC: G11C7/00 ,  G06F3/06 ,  G11C11/4074 ,  G06F1/26 ,  G11C5/14

CPC classification number: G06F3/0625 ,  G06F1/266 ,  G06F3/0634 ,  G06F3/0673 ,  G11C5/147 ,  G11C11/4074 ,  G11C2207/2227

Abstract: A memory system supports high-performance and low-power modes. The memory system includes a memory core and a core interface. The memory core employs core supply voltages that remain the same in both modes. Supply voltages and signaling rates for the core interface may be scaled down to save power. Level shifters between the memory core and core interface level shift signals as needed to accommodate the signaling voltages used by the core interface in the different modes.

Abstract translation: 内存系统支持高性能和低功耗模式。 存储器系统包括存储器核和核心接口。 存储器内核采用在两种模式下保持相同的核心电源电压。 核心接口的电源电压和信号速率可以缩小以节省功耗。 存储器核心和核心接口电平之间的电平移位器根据需要移位信号以适应不同模式下核心接口所使用的信令电压。

公开(公告)号：US20150281613A1

公开(公告)日：2015-10-01

申请号：US14433003

申请日：2013-09-30

Applicant: RAMBUS INC.

Inventor： Thomas Vogelsang ,  Michael Guidash ,  Song Xue

IPC: H04N5/378 ,  H04N5/376

CPC classification number: H04N5/378 ,  H04N5/3355 ,  H04N5/35536 ,  H04N5/35545 ,  H04N5/37455 ,  H04N5/3765

Abstract: An image sensor architecture with multi-bit sampling is implemented within an image sensor system. A pixel signal produced in response to light incident upon a photosensitive element is converted to a multiple-bit digital value representative of the pixel signal. If the pixel signal exceeds a sampling threshold, the photosensitive element is reset. During an image capture period, digital values associated with pixel signals that exceed a sampling threshold are accumulated into image data.

Abstract translation: 在图像传感器系统中实现具有多位采样的图像传感器架构。 响应于入射到感光元件上的光而产生的像素信号被转换成表示像素信号的多位数字值。 如果像素信号超过采样阈值，则光敏元件被复位。 在图像捕获期间，与超过采样阈值的像素信号相关联的数字值被累积到图像数据中。

公开(公告)号：US20150234707A1

公开(公告)日：2015-08-20

申请号：US14692092

申请日：2015-04-21

Applicant: Rambus Inc.

Inventor： Thomas Vogelsang ,  Suresh N. Rajan ,  Ian P. Shaeffer ,  Frederick A. Ware ,  Wayne F. Ellis

IPC: G06F11/10 ,  G11C29/44

CPC classification number: G06F11/1076 ,  G06F11/1048 ,  G06F11/108 ,  G11C11/40 ,  G11C29/24 ,  G11C29/42 ,  G11C29/44 ,  G11C29/50016

Abstract: A dynamic random access memory (DRAM) array is configured for selective repair and error correction of a subset of the array. Error-correcting code (ECC) is provided to a selected subset of the array to protect a row or partial row of memory cells where one or more weak memory cells are detected. By adding a sense amplifier stripe to the edge of the memory array, the adjacent edge segment of the array is employed to store ECC information associated with the protected subsets of the array. Bit replacement is also applied to defective memory cells. By implementing ECC selectively rather than to the entire array, integrity of the memory array is maintained at minimal cost to the array in terms of area and energy consumption.

Abstract translation: 动态随机存取存储器（DRAM）阵列被配置用于阵列的子集的选择性修复和纠错。 将纠错码（ECC）提供给阵列的选定子集，以保护检测到一个或多个弱存储器单元的行或部分行的存储单元。 通过向存储器阵列的边缘添加感测放大器条纹，阵列的相邻边缘段用于存储与阵列的受保护子集相关联的ECC信息。 位更换也适用于有缺陷的存储单元。 通过有选择地执行ECC而不是整个阵列，在面积和能量消耗方面，以阵列的最低成本保持存储器阵列的完整性。

公开(公告)号：US09037949B1

公开(公告)日：2015-05-19

申请号：US13846200

申请日：2013-03-18

Applicant: Rambus Inc.

Inventor： Thomas Vogelsang ,  Suresh N. Rajan ,  Ian P. Shaeffer ,  Frederick A. Ware ,  Wayne F. Ellis

IPC: G11C29/00 ,  G06F11/10

CPC classification number: G06F11/1076 ,  G06F11/1048 ,  G06F11/108 ,  G11C11/40 ,  G11C29/24 ,  G11C29/42 ,  G11C29/44 ,  G11C29/50016

Abstract: A dynamic random access memory (DRAM) array is configured for selective repair and error correction of a subset of the array. Error-correcting code (ECC) is provided to a selected subset of the array to protect a row or partial row of memory cells where one or more weak memory cells are detected. By adding a sense amplifier stripe to the edge of the memory array, the adjacent edge segment of the array is employed to store ECC information associated with the protected subsets of the array. Bit replacement is also applied to defective memory cells. By implementing ECC selectively rather than to the entire array, integrity of the memory array is maintained at minimal cost to the array in terms of area and energy consumption.

Abstract translation: 动态随机存取存储器（DRAM）阵列被配置用于阵列的子集的选择性修复和纠错。 将纠错码（ECC）提供给阵列的选定子集，以保护检测到一个或多个弱存储器单元的行或部分行的存储单元。 通过向存储器阵列的边缘添加感测放大器条纹，阵列的相邻边缘段用于存储与阵列的受保护子集相关联的ECC信息。 位更换也适用于有缺陷的存储单元。 通过有选择地执行ECC而不是整个阵列，在面积和能量消耗方面，以阵列的最低成本保持存储器阵列的完整性。