公开(公告)号：US20130196054A1

公开(公告)日：2013-08-01

申请号：US13803094

申请日：2013-03-14

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Shunpei Yamazaki ,  Hideaki Kuwabara

IPC: H05B33/10

CPC classification number: H05B33/10 ,  C23C14/12 ,  C23C14/24 ,  H01L51/001 ,  H01L51/5246 ,  H01L51/56 ,  H01L2251/5323

Abstract: A device having three evaporation sources and a unit for moving the respective evaporation sources in one chamber is used, whereby it becomes possible to increase efficiency of use of an evaporation material. Consequently, manufacturing cost can be reduced, and a uniform thickness can be obtained over an entire surface of a substrate even in the case in which a large area substrate is used.

Abstract translation: 使用具有三个蒸发源的装置和用于在一个室中移动各个蒸发源的单元，从而可以提高蒸发材料的使用效率。 因此，即使在使用大面积基板的情况下，也可以在基板的整个表面上获得均匀的厚度。

公开(公告)号：US20130175526A1

公开(公告)日：2013-07-11

申请号：US13784908

申请日：2013-03-05

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Shunpei Yamazaki ,  Miyuki HOSOBA ,  Junichiro Sakata ,  Hideaki Kuwabara

IPC: H01L29/786

CPC classification number: H01L29/78606 ,  G02F1/1339 ,  G02F1/134336 ,  G02F1/1345 ,  G02F1/136227 ,  G02F1/136286 ,  G02F1/1368 ,  G02F1/167 ,  G02F2001/13606 ,  G02F2201/123 ,  G09G3/344 ,  G09G3/3677 ,  G09G2300/0426 ,  G09G2310/0286 ,  G09G2310/08 ,  H01L27/1218 ,  H01L27/1225 ,  H01L27/124 ,  H01L27/1248 ,  H01L27/1255 ,  H01L27/1274 ,  H01L27/3262 ,  H01L29/45 ,  H01L29/513 ,  H01L29/518 ,  H01L29/66742 ,  H01L29/66969 ,  H01L29/786 ,  H01L29/78648 ,  H01L29/7869 ,  H01L29/78696

Abstract: An object is to provide a semiconductor device having a structure in which parasitic capacitance between wirings can be efficiently reduced. In a bottom gate thin film transistor using an oxide semiconductor layer, an oxide insulating layer used as a channel protection layer is formed above and in contact with part of the oxide semiconductor layer overlapping with a gate electrode layer, and at the same time an oxide insulating layer covering a peripheral portion (including a side surface) of the stacked oxide semiconductor layer is formed. Further, a source electrode layer and a drain electrode layer are formed in a manner such that they do not overlap with the channel protection layer. Thus, a structure in which an insulating layer over the source electrode layer and the drain electrode layer is in contact with the oxide semiconductor layer is provided.

公开(公告)号：US12197717B2

公开(公告)日：2025-01-14

申请号：US18212266

申请日：2023-06-21

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei Yamazaki ,  Hajime Kimura ,  Hideaki Kuwabara ,  Koji Dairiki

IPC: G06F3/0488 ,  G06F1/3234 ,  G06F3/041 ,  G06F3/044 ,  G06F3/04817 ,  G06F3/0482

Abstract: A data processing device which includes a flexible position input portion for sensing proximity or a touch of an object such as a user's palm and finger. In the case where a first region of the flexible position input portion is held by a user for a certain period, supply of image signals to the first region is selectively stopped.

公开(公告)号：US20230387136A1

公开(公告)日：2023-11-30

申请号：US18231902

申请日：2023-08-09

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei Yamazaki ,  Hiroki Ohara ,  Toshinari Sasaki ,  Kosei Noda ,  Hideaki Kuwabara

IPC: H01L27/12 ,  H01L29/786 ,  H01L29/51 ,  G02F1/1333 ,  G02F1/1337 ,  G02F1/1343 ,  G02F1/1362 ,  G02F1/1368 ,  H01L29/24

CPC classification number: H01L27/1225 ,  H01L29/78609 ,  H01L27/124 ,  H01L27/1248 ,  H01L27/1214 ,  H01L29/7869 ,  H01L29/517 ,  G02F1/133345 ,  G02F1/1337 ,  G02F1/134309 ,  G02F1/136227 ,  G02F1/136277 ,  G02F1/1368 ,  H01L29/24

Abstract: An object is to provide a semiconductor device having a structure with which parasitic capacitance between wirings can be sufficiently reduced. An oxide insulating layer serving as a channel protective layer is formed over part of an oxide semiconductor layer overlapping with a gate electrode layer. In the same step as formation of the oxide insulating layer, an oxide insulating layer covering a peripheral portion of the oxide semiconductor layer is formed. The oxide insulating layer which covers the peripheral portion of the oxide semiconductor layer is provided to increase the distance between the gate electrode layer and a wiring layer formed above or in the periphery of the gate electrode layer, whereby parasitic capacitance is reduced.

公开(公告)号：US11726378B2

公开(公告)日：2023-08-15

申请号：US17537958

申请日：2021-11-30

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei Yamazaki ,  Yukie Suzuki ,  Hideaki Kuwabara ,  Hajime Kimura

IPC: G02F1/1368 ,  G02F1/1339 ,  H01L29/66 ,  H01L27/12 ,  H01L29/04 ,  H01L29/786 ,  G02F1/1362 ,  G02F1/1333 ,  G02F1/1343 ,  H01L29/45 ,  H01L29/49

CPC classification number: G02F1/1368 ,  G02F1/1339 ,  G02F1/133345 ,  G02F1/134309 ,  G02F1/136286 ,  H01L27/1214 ,  H01L27/1222 ,  H01L27/1288 ,  H01L29/04 ,  H01L29/66765 ,  H01L29/78678 ,  H01L29/78696 ,  H01L29/458 ,  H01L29/4908

Abstract: A method of manufacturing, with high mass productivity, liquid crystal display devices having highly reliable thin film transistors with excellent electric characteristics is provided. In a liquid crystal display device having an inverted staggered thin film transistor, the inverted staggered thin film transistor is formed as follows: a gate insulating film is formed over a gate electrode; a microcrystalline semiconductor film which functions as a channel formation region is formed over the gate insulating film; a buffer layer is formed over the microcrystalline semiconductor film; a pair of source and drain regions are formed over the buffer layer; and a pair of source and drain electrodes are formed in contact with the source and drain regions so as to expose a part of the source and drain regions.

公开(公告)号：US11714542B2

公开(公告)日：2023-08-01

申请号：US17701953

申请日：2022-03-23

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei Yamazaki ,  Hajime Kimura ,  Hideaki Kuwabara ,  Koji Dairiki

IPC: G06F3/0488 ,  G06F1/3234 ,  G06F3/041 ,  G06F3/0482 ,  G06F3/04817 ,  G06F3/044

CPC classification number: G06F3/0488 ,  G06F1/3265 ,  G06F3/0412 ,  G06F3/0482 ,  G06F3/044 ,  G06F3/04817 ,  G06F2203/04101 ,  G06F2203/04104 ,  G06F2203/04108 ,  Y02B70/10 ,  Y02D10/00

Abstract: A data processing device which includes a flexible position input portion for sensing proximity or a touch of an object such as a user's palm and finger. In the case where a first region of the flexible position input portion is held by a user for a certain period, supply of image signals to the first region is selectively stopped.

公开(公告)号：US11194207B2

公开(公告)日：2021-12-07

申请号：US16912853

申请日：2020-06-26

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei Yamazaki ,  Yukie Suzuki ,  Hideaki Kuwabara ,  Hajime Kimura

IPC: G02F1/1368 ,  G02F1/1339 ,  H01L29/66 ,  H01L27/12 ,  H01L29/04 ,  H01L29/786 ,  G02F1/1362 ,  G02F1/1333 ,  G02F1/1343 ,  H01L29/45 ,  H01L29/49

Abstract: A method of manufacturing, with high mass productivity, liquid crystal display devices having highly reliable thin film transistors with excellent electric characteristics is provided. In a liquid crystal display device having an inverted staggered thin film transistor, the inverted staggered thin film transistor is formed as follows: a gate insulating film is formed over a gate electrode; a microcrystalline semiconductor film which functions as a channel formation region is formed over the gate insulating film; a buffer layer is formed over the microcrystalline semiconductor film; a pair of source and drain regions are formed over the buffer layer; and a pair of source and drain electrodes are formed in contact with the source and drain regions so as to expose a part of the source and drain regions.

公开(公告)号：US11177289B2

公开(公告)日：2021-11-16

申请号：US16662394

申请日：2019-10-24

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei Yamazaki ,  Junichiro Sakata ,  Hiroyuki Miyake ,  Hideaki Kuwabara ,  Tatsuya Takahashi

IPC: H01L27/12 ,  H01L29/45 ,  G02F1/1368 ,  H01L29/786 ,  H01L21/02

Abstract: An aperture ratio of a semiconductor device is improved. A driver circuit and a pixel are provided over one substrate, and a first thin film transistor in the driver circuit and a second thin film transistor in the pixel each include a gate electrode layer, a gate insulating layer over the gate electrode layer, an oxide semiconductor layer over the gate insulating layer, source and drain electrode layers over the oxide semiconductor layer, and an oxide insulating layer in contact with part of the oxide semiconductor layer over the gate insulating layer, the oxide semiconductor layer, and the source and drain electrode layers. The gate electrode layer, the gate insulating layer, the oxide semiconductor layer, the source and drain electrode layers, and the oxide insulating layer of the second thin film transistor each have a light-transmitting property.

公开(公告)号：US10957723B2

公开(公告)日：2021-03-23

申请号：US16847933

申请日：2020-04-14

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Toru Takayama ,  Junya Maruyama ,  Yuugo Goto ,  Hideaki Kuwabara ,  Shunpei Yamazaki

IPC: H01L21/00 ,  H01L27/12 ,  H01L21/762 ,  H01L27/32 ,  B60R1/00 ,  B60R11/02 ,  B60R11/04 ,  H01L21/683 ,  B60R11/00

Abstract: To provide a semiconductor device in which a layer to be peeled is attached to a base having a curved surface, and a method of manufacturing the same, and more particularly, a display having a curved surface, and more specifically a light-emitting device having a light emitting element attached to a base with a curved surface. A layer to be peeled, which contains a light emitting element furnished to a substrate using a laminate of a first material layer which is a metallic layer or nitride layer, and a second material layer which is an oxide layer, is transferred onto a film, and then the film and the layer to be peeled are curved, to thereby produce a display having a curved surface.

公开(公告)号：US20200286925A1

公开(公告)日：2020-09-10

申请号：US16881054

申请日：2020-05-22

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei Yamazaki ,  Jun Koyama ,  Hideaki Kuwabara ,  Saishi Fujikawa

IPC: H01L27/12 ,  H01L29/66 ,  G02F1/1345 ,  H01L27/15

Abstract: In a display device such as a liquid crystal display device, a large sized display screen is realized under low power consumption. A surface of a source wiring line of a pixel portion employed in an active matrix type liquid crystal display device is processed by way of a plating process operation so as to lower a resistance value of this source wiring line. The source wiring line of the pixel portion is manufactured at a step different from a step for manufacturing a source wiring line of a drive circuit portion. Further, electrodes of a terminal portion are processed by a plating process operation so as to reduce a resistance value thereof.