公开(公告)号：US20210020505A1

公开(公告)日：2021-01-21

申请号：US16797990

申请日：2020-02-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jaegwon Jang ,  Seokhyun Lee ,  Jongyoun Kim ,  Minjun Bae

IPC: H01L21/768 ,  H01L23/00 ,  H01L21/56

Abstract: A method of manufacturing a semiconductor package is provided including forming a lower redistribution layer. A conductive post is formed on the lower redistribution layer. A semiconductor chip is mounted on the lower redistribution layer. A molding member is formed on the lower redistribution layer. An upper surface of the molding member is at a level lower than an upper surface of the conductive post. An insulating layer is formed on the molding member. An upper surface of the insulating layer is at a level higher than the upper surface of the conductive post. The insulating layer is etched to expose the upper surface of the conductive post. An upper redistribution layer is formed on the insulating layer. The upper redistribution layer is electrically connected to the conductive post.

公开(公告)号：US10741518B2

公开(公告)日：2020-08-11

申请号：US16698117

申请日：2019-11-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Youn Ji Min ,  Seokhyun Lee ,  Jongyoun Kim ,  Kyoung Lim Suk ,  SeokWon Lee

IPC: H01L23/538 ,  H01L23/00 ,  H01L21/56 ,  H01L21/48 ,  H01L21/78 ,  H01L23/31 ,  H01L25/10 ,  H01L21/683 ,  H01L23/498

Abstract: A semiconductor package includes: a redistribution substrate; a semiconductor chip on the redistribution substrate; and an external terminal on a bottom surface of the redistribution substrate, wherein the redistribution substrate comprises: a first insulating layer including a first opening; a second insulating layer on the first insulating layer and including a second opening, wherein the second opening is positioned in the first opening in a plan view; a first barrier metal layer disposed along a sidewall of the first opening and along a sidewall of the second opening; a first redistribution conductive pattern on the first barrier metal layer; a third insulating layer on a bottom surface of the first insulating layer; and a pad penetrating the third insulating layer and electrically connecting to the first redistribution conductive pattern, wherein the external terminal is provided on the pad, wherein the second insulating layer at least partially covers a chip pad of the semiconductor chip, and the second opening at least partially exposes the chip pad, wherein, inside the second insulating layer, the first barrier metal layer is in contact with the chip pad through the second opening, and wherein the first redistribution conductive pattern has a surface roughness including protrusions extending in a range of from about 0.01 μm to about 0.5 μm, and the first insulating layer has a surface roughness smaller than the surface roughness of the first redistribution conductive pattern.

公开(公告)号：US20190181064A1

公开(公告)日：2019-06-13

申请号：US16279118

申请日：2019-02-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jongyoun Kim ,  Seokhyun Lee

IPC: H01L21/66 ,  H01L23/31 ,  H01L25/10 ,  H01L21/48 ,  H01L23/538 ,  H01L23/498

Abstract: A semiconductor package including a redistribution substrate, and a semiconductor chip mounted on the redistribution substrate, the semiconductor chip having a conductive pad on one surface thereof may be provided. The redistribution substrate may include a first passivation pattern on the conductive pad, the first passivation pattern exposing a portion of the conductive pad, and a redistribution pattern covering the portion of the conductive pad exposed by the first passivation pattern and surrounding the first passivation pattern.

公开(公告)号：US12300589B2

公开(公告)日：2025-05-13

申请号：US17405603

申请日：2021-08-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Gwangjae Jeon ,  Jung-Ho Park ,  Seokhyun Lee ,  Yaejung Yoon

IPC: H01L23/498 ,  H01L23/00 ,  H01L23/31

Abstract: Disclosed are semiconductor packages and methods of fabricating the same. The semiconductor package comprises a first redistribution substrate and a first semiconductor device on the first redistribution substrate. The first redistribution substrate includes a first dielectric layer that includes a first hole, an under-bump that includes a first bump part in the first hole and a second bump part that protrudes from the first bump part onto the first dielectric layer, an external connection terminal on a bottom surface of the first dielectric layer and connected to the under-bump through the first hole, a wetting layer between the external connection terminal and the under-bump, and a first barrier/seed layer between the under-bump and the first dielectric layer and between the under-bump and the wetting layer.

公开(公告)号：US12237256B2

公开(公告)日：2025-02-25

申请号：US18183062

申请日：2023-03-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kyoung Lim Suk ,  Keung Beum Kim ,  Dongkyu Kim ,  Minjung Kim ,  Seokhyun Lee

IPC: H01L23/48 ,  H01L21/48 ,  H01L23/498 ,  H01L23/538 ,  H01L25/10 ,  H01L23/00 ,  H01L25/065 ,  H01L25/18

Abstract: A semiconductor package includes a redistribution substrate and a semiconductor chip thereon. The redistribution substrate includes a ground under-bump pattern, signal under-bump patterns laterally spaced apart from the ground under-bump pattern, first signal line patterns disposed on the signal under-bump patterns and coupled to corresponding signal under-bump patterns, and a first ground pattern coupled to the ground under-bump pattern and laterally spaced apart from the first signal line pattern. Each of the signal and ground under-bump patterns includes a first part and a second part formed on the first part and that is wider than the first part. The second part of the ground under-bump pattern is wider than the second part of the signal under-bump pattern. The ground under-bump pattern vertically overlaps the first signal line patterns. The first ground pattern does not vertically overlap the signal under-bump patterns.

公开(公告)号：US12087744B2

公开(公告)日：2024-09-10

申请号：US18125170

申请日：2023-03-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dongkyu Kim ,  Seokhyun Lee ,  Yeonho Jang ,  Jaegwon Jang

IPC: H01L25/10 ,  H01L21/48 ,  H01L21/56 ,  H01L21/683 ,  H01L23/00 ,  H01L23/31 ,  H01L23/538 ,  H01L25/00

CPC classification number: H01L25/105 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/563 ,  H01L21/565 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/3128 ,  H01L23/3135 ,  H01L23/5383 ,  H01L23/5386 ,  H01L23/5389 ,  H01L23/562 ,  H01L24/19 ,  H01L24/20 ,  H01L24/48 ,  H01L25/50 ,  H01L2221/68372 ,  H01L2224/214 ,  H01L2224/215 ,  H01L2224/48227 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01079 ,  H01L2924/3511

Abstract: A semiconductor package device includes a first semiconductor package, a second semiconductor package, and first connection terminals between the first and second semiconductor packages. The first semiconductor package includes a lower redistribution substrate, a semiconductor chip, and an upper redistribution substrate vertically spaced apart from the lower redistribution substrate across the semiconductor chip. The upper redistribution substrate includes a dielectric layer, redistribution patterns vertically stacked in the dielectric layer and each including line and via parts, and bonding pads on uppermost redistribution patterns. The bonding pads are exposed from the dielectric layer and in contact with the first connection terminals. A diameter of each bonding pad decreases in a first direction from a central portion at a top surface of the upper redistribution substrate to an outer portion at the top surface thereof. A thickness of each bonding pad increases in the first direction.

公开(公告)号：US20240203960A1

公开(公告)日：2024-06-20

申请号：US18485378

申请日：2023-10-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seokhyun Lee

IPC: H01L25/10 ,  H01L23/00 ,  H10B80/00

CPC classification number: H01L25/105 ,  H01L24/16 ,  H01L24/32 ,  H01L24/33 ,  H01L24/73 ,  H10B80/00 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/33519 ,  H01L2224/73253 ,  H01L2225/1005 ,  H01L2924/1431 ,  H01L2924/1436 ,  H01L2924/1438

Abstract: A semiconductor package includes a first semiconductor chip, a connection die adjacent a side surface of the first semiconductor chip, and a second semiconductor chip on the first semiconductor chip and the connection die. The first semiconductor chip includes a plurality of first through electrodes. The connection die includes a plurality of second through electrodes. The first through electrodes and the second through electrodes are below and vertically overlap the second semiconductor chip.

公开(公告)号：US12015018B2

公开(公告)日：2024-06-18

申请号：US18060853

申请日：2022-12-01

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyeonjeong Hwang ,  Kyoung Lim Suk ,  Seokhyun Lee ,  Jaegwon Jang

IPC: H01L25/10 ,  H01L21/48 ,  H01L21/56 ,  H01L21/683 ,  H01L21/78 ,  H01L23/31 ,  H01L23/538 ,  H01L25/00

CPC classification number: H01L25/105 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/565 ,  H01L21/568 ,  H01L21/6835 ,  H01L21/78 ,  H01L23/3128 ,  H01L23/5383 ,  H01L23/5386 ,  H01L23/5389 ,  H01L25/50 ,  H01L2221/68372 ,  H01L2225/1035 ,  H01L2225/1058

Abstract: A semiconductor package includes a first redistribution substrate, a first semiconductor chip mounted on the first redistribution substrate, a first molding layer on the first redistribution substrate and covering a top surface and lateral surfaces of the first semiconductor chip, a second redistribution substrate on the first molding layer, and an adhesive film between the second redistribution substrate and the first molding layer. The adhesive film is spaced apart from the first semiconductor chip and covers a top surface of the first molding layer. A lateral surface of the adhesive film is coplanar with a lateral surface of the second redistribution substrate.

公开(公告)号：US12009350B2

公开(公告)日：2024-06-11

申请号：US18130760

申请日：2023-04-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyoung Lim Suk ,  Seokhyun Lee

IPC: H01L21/44 ,  H01L21/48 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H01L23/498 ,  H01L23/522 ,  H01L23/528 ,  H01L25/10

CPC classification number: H01L25/105 ,  H01L21/4857 ,  H01L21/486 ,  H01L21/565 ,  H01L23/3107 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49838 ,  H01L23/5226 ,  H01L23/5283 ,  H01L24/08 ,  H01L24/09 ,  H01L24/16 ,  H01L24/17 ,  H01L24/96 ,  H01L24/97 ,  H01L2224/0231 ,  H01L2224/02373 ,  H01L2224/02381 ,  H01L2224/08235 ,  H01L2224/16227 ,  H01L2224/96 ,  H01L2224/97 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/182

Abstract: A method of fabricating a semiconductor package includes providing a semiconductor chip, forming a redistribution substrate, and fabricating a package including the semiconductor chip disposed on the redistribution substrate. The forming of the redistribution substrate may include forming a first insulating layer on a substrate, the first insulating layer having a first opening formed therein, forming an integrally formed first redistribution pattern in the first opening and on the first insulating layer, forming a second insulating layer on the first insulating layer to cover the first redistribution pattern, and performing a planarization process on the second insulating layer to expose the first redistribution pattern.

公开(公告)号：US20240063103A1

公开(公告)日：2024-02-22

申请号：US18236090

申请日：2023-08-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Cheol Kim ,  Seokhyun Lee ,  Seokgeun Ahn ,  Hwanyoung Choi

IPC: H01L23/498 ,  H01L25/10 ,  H01L23/00 ,  H01L23/31

CPC classification number: H01L23/49822 ,  H01L25/105 ,  H01L23/49838 ,  H01L23/49894 ,  H01L24/08 ,  H01L24/16 ,  H01L23/3107 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2224/08235 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2924/1579 ,  H01L2924/15153 ,  H01L2924/15174 ,  H01L2924/15184

Abstract: A semiconductor package includes a first redistribution structure including a top surface, a chip arranged on the top surface of the first redistribution structure the chip having a top surface, bottom surface, and side surfaces, and a package body arranged on the top surface of the first redistribution structure to cover the side surfaces of the chip. The first redistribution structure includes a plurality of redistribution layers stacked in a vertical direction, a plurality of redistribution insulating layers stacked in the vertical direction and which insulate the plurality of redistribution layers from each other, a plurality of redistribution vias buried in a plurality of redistribution via holes penetrating the plurality of redistribution insulating layers and electrically connecting the plurality of redistribution layers to each other, and a plurality of self-formed barrier layers formed between side surfaces of the plurality of redistribution layers and the plurality of redistribution insulating layers.