Apparatus and method of updating filter tap coefficients of an equalizer
    61.
    发明授权
    Apparatus and method of updating filter tap coefficients of an equalizer 失效
    更新均衡器滤波器抽头系数的装置和方法

    公开(公告)号:US07394735B2

    公开(公告)日:2008-07-01

    申请号:US10429954

    申请日:2003-05-06

    IPC分类号: G11B7/004

    CPC分类号: G11B20/10009 G11B20/18

    摘要: An apparatus, a method, and a computer readable recording medium thereof to update filter tap coefficients of an equalizer include a defect signal detection unit and a coefficient updating unit. The defect signal detection unit receives a sampled input signal reflected from an optical disc and/or a track jump signal, detects whether the input signal and/or the track jump signal are defective, and outputs an update stop signal indicative thereof. The coefficient updating unit stops the updating of the filter tap coefficients in response to the update stop signal and outputs current filter tap coefficients.

    摘要翻译: 用于更新均衡器的滤波器抽头系数的装置,方法和计算机可读记录介质包括缺陷信号检测单元和系数更新单元。 缺陷信号检测单元接收从光盘反射的采样输入信号和/或轨道跳转信号,检测输入信号和/或轨道跳转信号是否有缺陷,并输出指示其的更新停止信号。 系数更新单元响应于更新停止信号停止更新滤波器抽头系数,并输出当前滤波器抽头系数。

    Nonvolatile memory device, layer deposition apparatus and method of fabricating a nonvolatile memory device using the same
    62.
    发明申请
    Nonvolatile memory device, layer deposition apparatus and method of fabricating a nonvolatile memory device using the same 审中-公开
    非挥发性存储器件,层淀积设备和使用其的非易失性存储器件的制造方法

    公开(公告)号:US20070196984A1

    公开(公告)日:2007-08-23

    申请号:US11655191

    申请日:2007-01-19

    IPC分类号: H01L21/336

    摘要: Provided are a nonvolatile memory device, a layer deposition apparatus and a method of fabricating a nonvolatile memory device using the same. The apparatus may include a chamber capable of holding a substrate, a particle-discharging target discharging particles toward the substrate, and a first ion beam gun accelerating a first plurality of ions and irradiating the accelerated ions toward the substrate. The method of fabricating a nonvolatile memory device may include discharging particles from a target toward a substrate, accelerating and irradiating a first plurality of ions toward the substrate, forming a reaction product by reacting the discharged particles and the accelerated and irradiated first plurality of ions, and forming a data storage layer having a deposited layer on the substrate. The nonvolatile memory device may include a data storage layer including a transition metal oxide layer formed by reacting discharged transition metal particles and accelerated and irradiated oxygen ions.

    摘要翻译: 提供一种非易失性存储器件,层淀积设备和使用其的非易失性存储器件的制造方法。 该装置可以包括能够保持基板的室,向基板排出颗粒的颗粒排放目标,以及加速第一多个离子并将加速离子朝向基板照射的第一离子束枪。 制造非易失性存储器件的方法可以包括将靶从靶向衬底排放,加速和照射第一多个离子朝向衬底,通过使排出的微粒和加速和照射的第一多个离子反应形成反应产物, 以及在所述基板上形成具有沉积层的数据存储层。 非易失性存储装置可以包括数据存储层,该数据存储层包括通过使放电的过渡金属颗粒和加速和照射的氧离子反应而形成的过渡金属氧化物层。

    Capacitor, semiconductor device having the same, and method of manufacturing the semiconductor device
    63.
    发明申请
    Capacitor, semiconductor device having the same, and method of manufacturing the semiconductor device 审中-公开
    具有相同的电容器,半导体器件以及半导体器件的制造方法

    公开(公告)号:US20070023810A1

    公开(公告)日:2007-02-01

    申请号:US11529611

    申请日:2006-09-29

    摘要: A semiconductor device with a stack type capacitor having a lower electrode formed of an aluminum-doped metal, and a manufacturing method thereof are provided. The semiconductor device includes: a semiconductor substrate having a gate structure and an active region; an interlayer dielectric film formed on the active region; a lower electrode formed of a metal containing aluminum on the interlayer dielectric film; a dielectric layer formed on the lower electrode; an upper electrode formed on the dielectric layer; and a plug formed in the interlayer dielectric film to electrically connect the active region with the lower electrode. The method includes: forming a gate structure and an active region on a semiconductor substrate; forming an interlayer dielectric film on the resultant semiconductor substrate; forming a plug in the interlayer dielectric film to electrically connect with the active region; forming a mold oxidation layer on the plug and the interlayer dielectric film; patterning the mold oxidation layer with a predetermined pattern and forming a lower electrode of material containing aluminum on the plug; and sequentially forming a dielectric layer and an upper electrode on the lower electrode.

    摘要翻译: 提供具有由铝掺杂金属形成的下电极的堆叠型电容器的半导体器件及其制造方法。 半导体器件包括:具有栅极结构和有源区的半导体衬底; 形成在有源区上的层间绝缘膜; 在层间电介质膜上由含有铝的金属形成的下电极; 形成在下电极上的电介质层; 形成在电介质层上的上电极; 以及形成在所述层间电介质膜中以将所述有源区电连接到所述下电极的插塞。 该方法包括:在半导体衬底上形成栅极结构和有源区; 在所得半导体衬底上形成层间绝缘膜; 在所述层间电介质膜中形成插塞以与所述有源区电连接; 在插塞和层间电介质膜上形成模具氧化层; 以预定图案图案化模具氧化层,并在插头上形成含有铝的材料的下电极; 并且在下电极上依次形成电介质层和上电极。

    Chemical vapor deposition method using alcohol for forming metal oxide thin film

    公开(公告)号:US07135207B2

    公开(公告)日:2006-11-14

    申请号:US10355221

    申请日:2003-01-31

    IPC分类号: C23C16/18

    CPC分类号: C23C16/40 C23C16/45553

    摘要: Provided is a method for fabricating a metal oxide thin film in which a metal oxide generated by a chemical reaction between a first reactant and a second reactant is deposited on the surface of a substrate as a thin film. The method involves introducing a first reactant containing a metal-organic compound into a reaction chamber including a substrate; and introducing a second reactant containing alcohol. Direct oxidation of a substrate or a deposition surface is suppressed by a reactant gas during the deposition process, as it uses alcohol vapor including no radical oxygen as a reactant gas for the deposition of a thin film. Also, since the thin film is deposited by the thermal decomposition, which is caused by the chemical reaction between the alcohol vapor and a precursor, the deposition rate is fast. Particularly, the deposition rate is also fast when a metal-organic complex with β-diketone ligands is used as a precursor. Further, a thin film with low leakage current can be obtained as the metal oxide thin film fabrication method using a chemical vapor deposition or atomic layer deposition method grows a thin film with fine microstructure.

    Alignment system used in nano-imprint lithography and nano imprint lithography method using the alignment system
    65.
    发明申请
    Alignment system used in nano-imprint lithography and nano imprint lithography method using the alignment system 审中-公开
    对准系统用于纳米压印光刻和纳米压印光刻法使用对准系统

    公开(公告)号:US20060172229A1

    公开(公告)日:2006-08-03

    申请号:US11340696

    申请日:2006-01-27

    IPC分类号: H01L21/00 G03C5/00

    摘要: An alignment system used in nano-imprint lithography and a nano-imprint lithography method using the alignment system are provided. The alignment system includes: a plurality of electron emission devices, which are provided in the mold and emit electrons; and a plurality of electrodes, which are provided to face the electron emission devices and at which the electrons emitted from the electron emission devices arrive. The mold and the substrate are aligned with each other by maximizing the amount of current in each of the electrodes.

    摘要翻译: 提供了用于纳米压印光刻的对准系统和使用对准系统的纳米压印光刻方法。 对准系统包括:多个电子发射装置,其设置在模具中并发射电子; 以及设置成面对电子发射器件并且从电子发射器件发射的电子到达的多个电极。 通过使每个电极中的电流量最大化,模具和衬底彼此对准。

    Ge precursor, GST thin layer formed using the same, phase-change memory device including the GST thin layer, and method of manufacturing the GST thin layer
    66.
    发明申请
    Ge precursor, GST thin layer formed using the same, phase-change memory device including the GST thin layer, and method of manufacturing the GST thin layer 有权
    Ge前体,使用相同的GST薄层,包括GST薄层的相变存储器件,以及制造GST薄层的方法

    公开(公告)号:US20060138393A1

    公开(公告)日:2006-06-29

    申请号:US11253693

    申请日:2005-10-20

    IPC分类号: H01L29/02

    摘要: Provided are a Ge precursor for low temperature deposition containing Ge, N, and Si, a GST thin layer doped with N and Si formed using the same, a memory device including the GST thin layer doped with N and Si, and a method of manufacturing the GST thin layer. The Ge precursor for low temperature deposition contains N and Si such that the temperature at which the Ge precursor is deposited to form a thin layer, particularly, the GST thin layer doped with N and Si, can be low. In addition, during the low temperature deposition, H2 plasma can be used. The GST phase-change layer doped with N and Si formed from the Ge precursor for low temperature deposition has a low reset current. Therefore, a memory device including the GST phase-change layer doped with N and Si can be highly integrated, have a high capacity, and can be operated at a high speed.

    摘要翻译: 提供了包含Ge,N和Si的低温沉积的Ge前体,掺杂有使用其形成的N和Si的GST薄层,包括掺杂有N和Si的GST薄层的存储器件,以及制造方法 GST薄层。 用于低温沉积的Ge前体包含N和Si,使得Ge前体沉积形成薄层的温度,特别是掺杂有N和Si的GST薄层的温度可以低。 此外,在低温沉积期间,可以使用H 2 O 3等离子体。 掺杂有由Ge前体形成的用于低温沉积的N和Si的GST相变层具有低复位电流。 因此,包含掺杂有N和Si的GST相变层的存储器件可以高度集成,具有高容量,并且可以高速运行。

    Non-volatile memory device including dummy electrodes and method of fabricating the same
    70.
    发明授权
    Non-volatile memory device including dummy electrodes and method of fabricating the same 有权
    包括虚拟电极的非易失性存储器件及其制造方法

    公开(公告)号:US08748969B2

    公开(公告)日:2014-06-10

    申请号:US12654470

    申请日:2009-12-22

    IPC分类号: H01L29/792

    摘要: Provided are a non-volatile memory device and a method of fabricating the same. The non-volatile memory device may include a substrate and a plurality of semiconductor pillars on the substrate. A plurality of control gate electrodes may be stacked on the substrate and intersecting the plurality of semiconductor pillars. A plurality of dummy electrodes may be stacked adjacent to the plurality of control gate electrodes on the substrate, the plurality of dummy electrodes being spaced apart from the plurality of control gate electrodes. A plurality of via plugs may be connected to the plurality of control gate electrodes. A plurality of wordlines may be on the plurality of via plugs. Each of the plurality of via plugs may penetrate a corresponding one of the plurality of control gate electrodes and at least one of the plurality of dummy electrodes.

    摘要翻译: 提供了一种非易失性存储器件及其制造方法。 非易失性存储器件可以包括衬底和衬底上的多个半导体柱。 多个控制栅电极可以堆叠在基板上并与多个半导体柱相交。 多个虚设电极可以与基板上的多个控制栅电极相邻,多个虚设电极与多个控制栅电极间隔开。 多个通孔塞可以连接到多个控制栅电极。 多个字线可以在多个通孔插头上。 多个通孔塞中的每一个可以穿透多个控制栅电极中的相应一个和多个虚拟电极中的至少一个。