公开(公告)号：US06720837B2

公开(公告)日：2004-04-13

申请号：US10254620

申请日：2002-09-25

申请人： Kouichi Moriya ,  Kuichi Kubo ,  Katsuyuki Sato ,  Yoshinori Narita

发明人： Kouichi Moriya ,  Kuichi Kubo ,  Katsuyuki Sato ,  Yoshinori Narita

IPC分类号： H03B532

CPC分类号： H03B5/368 ,  H01L2924/16195

摘要： A surface mounting quartz crystal oscillator has an IC chip containing an oscillator circuit, and a quartz crystal unit which are sealed in a container body by a metal cover, wherein stray capacitances C1, C2 are equivalently in parallel with oscillation capacitors Ca, Cb connected to one and the other ends of the crystal unit, respectively. A gap between the IC chip and a crystal blank of the crystal unit, and a gap between the crystal blank and metal cover are set in accordance with a changing amount of the oscillation frequency due to a change in the stray capacitances C1, C2 in a direction in which a change in equivalent series capacitance is reduced, as viewed from the crystal unit, while maintaining a spacing between the IC chip and metal cover.

摘要翻译： 表面安装石英晶体振荡器具有含有振荡电路的IC芯片和通过金属盖密封在容器主体中的石英晶体单元，其中杂散电容C1，C2等效地与连接到 分别是晶体单元的一端和另一端。 根据由于杂散电容C1，C2的变化引起的振荡频率的变化量，设定晶体单元的IC芯片和晶体坯料之间的间隙以及晶体坯料与金属盖板之间的间隙 在从晶体单元观察时，等效串联电容的变化减小的方向，同时保持IC芯片和金属盖之间的间隔。

公开(公告)号：USRE37176E1

公开(公告)日：2001-05-15

申请号：US09256500

申请日：1999-02-23

申请人： Kazuhiko Kajigaya ,  Katsuyuki Sato

发明人： Kazuhiko Kajigaya ,  Katsuyuki Sato

IPC分类号： G11C700

CPC分类号： G11C11/4096

摘要： A dynamic RAM is arranged such that a common data line in each of the non-selected ones of the divided memory arrays is connected to a pair of common source lines of a sense amplifier corresponding to the memory array concerned, whereby the potential of the common data line is set at a medium level which is substantially equal to the potential of the data lines by utilizing the medium potential of the pair of common source lines and a relatively large parasitic capacity thereof, thereby maintaining the data lines at the half-precharge level. The pair of common source lines are shorted to each other during the non-select period of the memory arrays, so that the common source lines have a medium level which is substantially equal to the half-precharge level of the data lines.

摘要翻译： 动态RAM被布置成使得分开的存储器阵列中的每个未选择的存储器阵列中的公共数据线连接到与所涉及的存储器阵列相对应的读出放大器的一对公共源极线，由此共同的 数据线通过利用一对公共源极线的中等电位和相对较大的寄生电容而设定在基本上等于数据线的电位的中间电平，从而将数据线保持在半预充电电平 。 这些公共源极线在存储器阵列的非选择周期期间彼此短路，使得公共源极线具有基本上等于数据线的半预充电电平的中等电平。

公开(公告)号：US5313423A

公开(公告)日：1994-05-17

申请号：US754019

申请日：1991-09-03

申请人： Katsuyuki Sato ,  Miki Matsumoto ,  Sadayuki Ohkuma ,  Masahiro Ogata ,  Masahiro Yoshida

发明人： Katsuyuki Sato ,  Miki Matsumoto ,  Sadayuki Ohkuma ,  Masahiro Ogata ,  Masahiro Yoshida

IPC分类号： G11C29/00 ,  G11C7/10 ,  G11C7/18 ,  G11C8/10 ,  G11C11/401 ,  G11C29/04 ,  G11C13/00

CPC分类号： G11C7/18 ,  G11C7/1075 ,  G11C8/10

摘要： A multiport memory is provided which permits both random access and serial access. In order to reduce parasitic capacitance and improve operating speed, the serial input/output lines are each divided into two parts at their middle points. Sense amplifiers for the serial input/output lines are provided at upper and lower ends of the serial access memory elements to respectively amplify signals from the divided lines. Additional features are provided for improving both the serial and random operation. For example, during the serial read mode, the column selector for random access is simultaneously operated, and read data passing through the random access column selector is used as head data for the serial output operation to be delivered through the serial output circuit. Also, a serial selector can be controlled by a select signal formed by a Gray Code counter to improve operating speed. Further features included a redundancy system for relief of defective bits, the use of common bit lines to improve integration density and an improved refreshing arrangement to reduce power consumption during the refresh mode.

公开(公告)号：US5187685A

公开(公告)日：1993-02-16

申请号：US749851

申请日：1991-08-26

申请人： Katsuyuki Sato ,  Hiroshi Kawamoto ,  Kazumasa Yanagisawa

发明人： Katsuyuki Sato ,  Hiroshi Kawamoto ,  Kazumasa Yanagisawa

IPC分类号： G11C11/4074 ,  G11C29/50

CPC分类号： G11C29/50016 ,  G11C11/4074 ,  G11C29/50 ,  G11C11/401 ,  G11C2029/5004

摘要： A voltage generating circuit having a voltage dividing circuit of complementary MISFETs is provided in an arrangement wherein a controlled output voltage, such as a bias voltage applied to plate electrodes of storage cells in a RAM, is obtained. The voltage dividing circuit has a series arrangement, between the power source voltage and a predetermined voltage, such as ground potential, of a first resistance, a first diode-connected MISFET, a second resistance and a second diode connected MISFET. Also, the voltage generator circuit has a first output MISFET of a first channel conductivity type having its gate coupled to the common connection of the first diode-connected MISFET and first resistance as well as a second output MISFET of the second conductivity type in series therewith which has a gate coupled to the common connection of the second diode-connected MISFET and second resistance. The first and second output MISFETs have their drains respectively coupled to receive the power source voltage and predetermined voltage and the source of the first output MISFET is coupled with the source of the second output MISFET wherein an output voltage of about 1/2 the potential of the power source voltage is obtained.

摘要翻译： 具有互补MISFET的分压电路的电压产生电路被提供在其中获得诸如施加到RAM中的存储单元的板电极的偏置电压的受控输出电压的布置中。 分压电路具有电源电压和第一电阻，第一二极管连接的MISFET，第二电阻和第二二极管连接的MISFET的预定电压（例如接地电位）之间的串联布置。 此外，电压发生器电路具有第一沟道导电类型的第一输出MISFET，其栅极连接到第一二极管连接的MISFET和第一电阻的公共连接以及与其串联的第二导电类型的第二输出MISFET。 其具有耦合到第二二极管连接的MISFET和第二电阻的公共连接的栅极。 第一和第二输出MISFET的漏极分别耦合以接收电源电压和预定电压，并且第一输出MISFET的源极与第二输出MISFET的源耦合，其中输出电压约为 获得电源电压。

公开(公告)号：US5161120A

公开(公告)日：1992-11-03

申请号：US496531

申请日：1990-03-20

申请人： Takeshi Kajimoto ,  Yutaka Shimbo ,  Katsuyuki Sato ,  Masahiro Ogata ,  Kanehide Kenmizaki ,  Shouji Kubono ,  Nobuo Kato ,  Kiichi Manita ,  Michitaro Kanamitsu

发明人： Takeshi Kajimoto ,  Yutaka Shimbo ,  Katsuyuki Sato ,  Masahiro Ogata ,  Kanehide Kenmizaki ,  Shouji Kubono ,  Nobuo Kato ,  Kiichi Manita ,  Michitaro Kanamitsu

IPC分类号： G01R31/26 ,  G01R31/28 ,  G11C11/401 ,  G11C11/403 ,  G11C11/406 ,  G11C11/407 ,  G11C11/408 ,  G11C11/409 ,  G11C11/4093 ,  G11C29/00 ,  G11C29/02 ,  G11C29/14 ,  G11C29/50 ,  H01L21/82 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/04 ,  H01L27/10 ,  H01L27/108 ,  H03K3/037 ,  H03K19/096

CPC分类号： G11C29/027 ,  G11C11/406 ,  G11C11/4093 ,  G11C29/02 ,  G11C29/50 ,  G11C29/50012 ,  G11C29/50016 ,  G11C2029/5004

摘要： A data output buffer is provided in connection with a semiconductor memory, such as a pseudostatic RAM, which is capable of high speed operation with respect to memory data readout. The buffer includes a latch circuit comprising a pair of NAND gate circuits having input and output terminals connected in cross connection, a pair of precharge MOSFETs provided respectively between the noninverted and inverted input terminals of the latch circuit, a pair of CMOS NAND gates which transfer the inverted signal of the latch circuit according to an inverted timing signal and a pair of series-connected MOSFETs effecting a pull-up/pull-down arrangement which receives the inverted signal of the output signal of the NAND gates.

摘要翻译： 数据输出缓冲器与诸如伪稳态RAM的半导体存储器相关地提供，其能够相对于存储器数据读出而进行高速操作。 该缓冲器包括一个锁存电路，该锁存电路包括一对具有交叉连接的输入和输出端的NAND门电路，分别设置在锁存电路的非反相和反相输入端之间的一对预充电MOSFET，一对转换 根据反相定时信号的锁存电路的反相信号和实现上拉/下拉布置的一对串联MOSFET，其接收NAND门输出信号的反相信号。

公开(公告)号：US5146573A

公开(公告)日：1992-09-08

申请号：US426781

申请日：1989-10-25

申请人： Katsuyuki Sato ,  Tadahiko Nishimukai ,  Kunio Uchiyama ,  Hirokazu Aoki ,  Susumu Hatano ,  Kanji Oishi ,  Hiroshi Fukuta ,  Takashi Kikuchi ,  Yasuhiko Saigou

发明人： Katsuyuki Sato ,  Tadahiko Nishimukai ,  Kunio Uchiyama ,  Hirokazu Aoki ,  Susumu Hatano ,  Kanji Oishi ,  Hiroshi Fukuta ,  Takashi Kikuchi ,  Yasuhiko Saigou

IPC分类号： G06F12/08 ,  G11C11/4096

CPC分类号： G11C11/4096 ,  G06F12/0804

摘要： In a cache memory setup, a buffer register is provided to accommodate the data read from a data memory. Between the buffer register and the data memory is connected a selector. This selector selectively transfers to the buffer register part of the data read from the data memory. The remaining part of the data is replaced with appropriate data for transfer to the buffer register. This arrangement provides the cache memory with a partial-write function.

摘要翻译： 在缓存存储器设置中，提供缓冲寄存器以容纳从数据存储器读取的数据。 在缓冲寄存器和数据存储器之间连接一个选择器。 该选择器选择性地将从数据存储器读取的数据传送到缓冲寄存器部分。 数据的剩余部分被替换为适当的数据以传送到缓冲寄存器。 这种布置为高速缓冲存储器提供部分写入功能。

公开(公告)号：US4961166A

公开(公告)日：1990-10-02

申请号：US729859

申请日：1985-05-02

申请人： Katsuyuki Sato ,  Kazumasa Yanagisawa ,  Kunio Ono

发明人： Katsuyuki Sato ,  Kazumasa Yanagisawa ,  Kunio Ono

IPC分类号： G11C11/4096 ,  G11C11/4099

CPC分类号： G11C11/4096 ,  G11C11/4099

摘要： A dynamic RAM, in which the difference between a data signal level from one of a pair of complementary data lines coupled to a memory cell and a reference potential level of the other of the complementary data lines is differentially amplified by a sense amplifier. The data line taking the reference potential level is coupled to the other data line through a switch element so that its data line capacitance is increased. As a result, the reference potential level is held at a relatively stable level irrespective of a leakage current such as that caused by .alpha. particles. This construction makes it possible to use a full-size dummy cell because the capacitance of the data lines which takes the reference potential level is increased. The reference potential level achieved by the use of the full-size dummy cell is made relatively accurate because of the relative accuracy between the capacitances of the memory cells and the capacitance of the full-size dummy cell.

摘要翻译： 动态RAM，其中来自耦合到存储单元的一对互补数据线中的一个的数据信号电平与另一个互补数据线的参考电位电平之间的差异由读出放大器差分放大。 采用参考电位电平的数据线通过开关元件耦合到另一条数据线，使其数据线电容增加。 结果，不管诸如由α粒子引起的漏电流如何，基准电位电平保持在相对稳定的水平。 这种结构使得可以使用全尺寸虚拟单元，因为增加了参考电位电平的数据线的电容。 由于存储单元的电容与全尺寸虚拟单元的电容之间的相对精度相对较高，因此通过使用全尺寸虚拟单元实现的参考电位水平相对精确。

公开(公告)号：US4893277A

公开(公告)日：1990-01-09

申请号：US255314

申请日：1988-10-11

申请人： Kazuhiko Kajigaya ,  Katsuyuki Sato

发明人： Kazuhiko Kajigaya ,  Katsuyuki Sato

IPC分类号： G11C11/401 ,  G11C11/409 ,  G11C11/4096

CPC分类号： G11C11/4096

摘要： A dynamic RAM is arranged such that a common data line in each of the non-selected ones of the divided memory arrays is connected to a pair of common source lines of a sense amplifier corresponding to the memory array concerned, whereby the potential of the common data line is set at a medium level which is substantially equal to the potential of the data lines by utilizing the medium potential of the pair of common source lines and a relatively large parasitic capacity thereof, thereby maintaining the data lines at the half-precharge level. The pair of common source lines are shorted to each other during the non-select period of the memory arrays, so that the common source lines have a medium level which is substantially equal to the half-precharge level of the data lines.

公开(公告)号：US4772628A

公开(公告)日：1988-09-20

申请号：US946202

申请日：1986-12-24

申请人： Norihiro Kakimoto ,  Nobuo Tanaka ,  Isao Sato ,  Katsuyuki Sato

发明人： Norihiro Kakimoto ,  Nobuo Tanaka ,  Isao Sato ,  Katsuyuki Sato

IPC分类号： C07F7/30 ,  A01N9/00 ,  C07D7/30

CPC分类号： C07F7/30

摘要： This invention discloses organogermanium compounds characterized in being expressed by the following formula: ##STR1## wherein R.sub.1, R.sub.2 and R.sub.3 respectively denote a hydrogen atom, a lower alkyl group, or a substituted or unsubstituted phenyl group, Y denotes an oxygen or sulfur atom, and Z denotes a hydroxyl group, an amino, or a lower alkoxy group, and antitumor agents comprising as a principal agent these compounds.

摘要翻译： 本发明公开了以下式表示的有机锗化合物：其中R1，R2和R3分别表示氢原子，低级烷基或取代或未取代的苯基，Y表示氧或 硫原子，Z表示羟基，氨基或低级烷氧基，以及包含作为主要试剂的这些化合物的抗肿瘤剂。

公开(公告)号：US4758995A

公开(公告)日：1988-07-19

申请号：US820326

申请日：1986-01-21

申请人： Katsuyuki Sato

发明人： Katsuyuki Sato

IPC分类号： G11C11/401 ,  G06F12/02 ,  G11C7/00 ,  G11C11/409 ,  G11C11/4096 ,  G11C8/00

CPC分类号： G11C11/4096

摘要： An improved DRAM having a plurality of main amplifiers for amplifying and storing signals read out to a plurality of common data lines in accordance with an internal address signal; a main amplifier control circuit for outputting the outputs of the main amplifiers sequentially in synchronism with changes in a column address strobe signal; an address counter for performing an addressing operation midway in the sequential reading operations of the plural main amplifiers; and a column selecting circuit for switching column switches in accordance with the address counter to cause data to be read out continuously at a high speed by extending a nibble mode.

摘要翻译： 一种改进的DRAM，具有多个主放大器，用于根据内部地址信号放大并存储读出到多个公共数据线的信号; 主放大器控制电路，用于与列地址选通信号的变化同步地顺序地输出主放大器的输出; 用于在多个主放大器的顺序读取操作中中途进行寻址操作的地址计数器; 以及列选择电路，用于根据地址计数器切换列开关，以通过扩展半字节模式以高速连续读出数据。