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公开(公告)号：US20110062550A1
公开(公告)日：2011-03-17
申请号：US12718691
申请日：2010-03-05
CPC分类号： H01L21/76843 , H01L27/11509 , H01L28/57
摘要： An integrated circuit containing a FeCap array. The FeCap array is at least partially surrounded on the sides by hydrogen barrier walls and on the top by a hydrogen barrier top plate. A method for at least partially enclosing a FeCap array with hydrogen barrier walls and a hydrogen barrier top plate.
摘要翻译： 包含FeCap阵列的集成电路。 FeCap阵列在侧面至少部分地被氢阻挡壁包围，并且在顶部被氢阻挡顶板包围。 一种用于至少部分地封闭具有氢阻挡壁和氢阻挡顶板的FeCap阵列的方法。
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公开(公告)号：US20100296329A1
公开(公告)日：2010-11-25
申请号：US12781601
申请日：2010-05-17
摘要： Non-volatile latch circuits, such as in memory cells and flip-flops, that are constructed for reliability screening. The non-volatile latch circuits each include ferroelectric capacitors coupled to storage nodes, for example at the outputs of cross-coupled inverters. Separate plate lines are connected to the ferroelectric capacitors of the complementary storage nodes. A time-zero test of the latch stability margin is performed by setting a logic state at the storage nodes, then programming the state into the ferroelectric capacitors by polarization. After power-down, the plate lines are biased with a differential voltage relative to one another, and the latch is then powered up to attempt recall of the programmed state. The differential voltage disturbs the recall, and provides a measure of the cell margin and its later-life reliability.
摘要翻译： 构建用于可靠性筛选的非易失性锁存电路，例如在存储器单元和触发器中。 非易失性锁存电路各自包括耦合到存储节点的铁电电容器，例如在交叉耦合的反相器的输出端。 单独的板线连接到互补存储节点的铁电电容器。 通过在存储节点设置逻辑状态，然后通过极化将状态编程到铁电电容器中来执行锁存稳定裕度的时间零测试。 掉电后，电路板以相对于彼此的差分电压偏置，然后锁存器上电以尝试调用编程状态。 差分电压会干扰召回，并提供信号余量的测量及其后期寿命的可靠性。
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公开(公告)号：US20100041232A1
公开(公告)日：2010-02-18
申请号：US12460602
申请日：2009-07-21
IPC分类号： H01L21/3205 , H01L21/02
CPC分类号： G06F17/5072 , G06F17/5068 , G06F2217/12 , H01L22/26 , H01L27/0207 , H01L27/11507 , Y02P90/265
摘要： A method of placing a dummy fill layer on a substrate is disclosed (FIG. 2). The method includes identifying a sub-region of the substrate (210). A density of a layer in the sub-region is determined (212). A pattern of the dummy fill layer is selected to produce a predetermined density (216). The selected pattern is placed in the sub-region (208).
摘要翻译： 公开了一种在衬底上放置虚拟填充层的方法（图2）。 该方法包括识别衬底（210）的子区域。 确定子区域中的层的密度（212）。 选择虚拟填充层的图案以产生预定的密度（216）。 所选择的图案被放置在子区域（208）中。
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64.发明申请Increasing Exposure Tool Alignment Signal Strength for a Ferroelectric Capacitor Layer 有权增加铁电电容层的曝光工具对准信号强度公开(公告)号：US20090243123A1
公开(公告)日：2009-10-01
申请号：US12411914
申请日：2009-03-26
IPC分类号： H01L23/544 , H01L21/31
CPC分类号： H01L23/544 , G03F9/7076 , G03F9/7084 , H01L2223/54453 , H01L2924/0002 , Y10T29/42 , H01L2924/00
摘要： An improved alignment structure for photolithographic pattern alignment is disclosed. A topographical alignment mark in an IC under a low reflectivity layer may be difficult to register. A reflective layer is formed on top of the low reflectivity layer so that the topography of the alignment mark is replicated in the reflective layer, enabling registration of the alignment mark using common photolithographic scanners and steppers. The reflective layer may be one or more layers, and may be metallic, dielectric or both. The reflective layer may be global over the entire IC or may be local to the alignment mark area. The reflective layer may be removed during subsequent processing, possibly with assist from an added etch stop layer, or may remain in the completed IC. The disclosed alignment mark structure is applicable to an IC with a stack of ferroelectric capacitor materials.
摘要翻译： 公开了用于光刻图案对准的改进的对准结构。 在低反射率层下的IC中的地形对准标记可能难以注册。 在低反射层的顶部形成反射层，使得对准标记的形貌在反射层中复制，使得能够使用普通的光刻扫描器和步进器对准对准标记。 反射层可以是一个或多个层，并且可以是金属的，电介质的或两者的。 反射层可以在整个IC上是全局的，或者可以是对准标记区域的局部。 可以在随后的处理期间去除反射层，可能来自添加的蚀刻停止层的辅助，或者可以保留在完整的IC中。 所公开的对准标记结构可应用于具有堆叠铁电电容器材料的IC。
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公开(公告)号：US20090243122A1
公开(公告)日：2009-10-01
申请号：US12185003
申请日：2008-08-01
IPC分类号： H01L23/544 , H01L21/76
CPC分类号： H01L23/544 , H01L2223/54426 , H01L2223/54453 , H01L2223/5448 , H01L2924/0002 , H01L2924/00
摘要： An IC alignment mark in a contact metal layer for use under an opaque layer, and a process for forming the alignment mark, are disclosed. The alignment mark includes contact metal fields, each several microns wide, with an array of PMD pillars in the interior, formed during contact etch, contact metal deposition and selective contact metal removal processes. The pillars are arrayed such that all exposed surfaces of the contact metal are planar. One configuration is a rectangular array in which every other row is laterally offset by one-half of the column spacing. Horizontal dimensions of the pillars are selected to maximize the contact metal fill factor, while providing sufficient adhesion to the underlying substrate during processing. The contact metal is at least 15 nanometers lower than the PMD layer surrounding the alignment mark, as a result of the contact metal removal process.
摘要翻译： 公开了在不透明层下使用的接触金属层中的IC对准标记和用于形成对准标记的工艺。 对准标记包括几微米宽的接触金属场，在接触蚀刻期间形成的PMD柱阵列，接触金属沉积和选择性接触金属去除过程。 柱子被排列成使得接触金属的所有暴露表面是平面的。 一个配置是矩形阵列，其中每隔一行被横向偏移列间距的一半。 选择柱的水平尺寸以使接触金属填充因子最大化，同时在处理期间向下面的基底提供足够的粘附。 作为接触金属去除过程的结果，接触金属比围绕对准标记的PMD层低至少15纳米。
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66.发明授权Mitigation of edge degradation in ferroelectric memory devices through plasma etch clean 有权通过等离子体蚀刻清洁减轻铁电存储器件中的边缘退化公开(公告)号：US07572698B2
公开(公告)日：2009-08-11
申请号：US11442810
申请日：2006-05-30
IPC分类号： H01L21/336
CPC分类号： H01L21/31122 , H01L21/0206 , H01L21/02071 , H01L21/32136 , H01L27/11502 , H01L28/55 , H01L28/65
摘要： A ferroelectric memory device is fabricated while mitigating edge degradation. A bottom electrode is formed over one or more semiconductor layers. A ferroelectric layer is formed over the bottom electrode. A top electrode is formed over the ferroelectric layer. The top electrode, the ferroelectric layer, and the bottom electrode are patterned or etched. A dry clean is performed that mitigates edge degradation. A wet etch/clean is then performed.
摘要翻译： 制造铁电存储器件，同时减轻边缘退化。 在一个或多个半导体层上形成底部电极。 在底部电极上形成铁电层。 顶部电极形成在铁电层上。 上电极，铁电层和底电极被图案化或蚀刻。 进行干洗以减轻边缘退化。 然后进行湿蚀刻/清洁。
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67.发明授权公开(公告)号：US06982448B2
公开(公告)日：2006-01-03
申请号：US10803445
申请日：2004-03-18
CPC分类号： H01L27/11507 , H01L28/57
摘要： Hydrogen barriers and fabrication methods are provided for protecting ferroelectric capacitors (CFE) from hydrogen diffusion in semiconductor devices (102), wherein nitrided aluminum oxide (N—AlOx) is formed over a ferroelectric capacitor (CFE), and one or more silicon nitride layers (112, 117) are formed over the nitrided aluminum oxide (N—AlOx). Hydrogen barriers are also provided in which an aluminum oxide (AlOx, N—AlOx) is formed over the ferroelectric capacitors (CFE), with two or more silicon nitride layers (112, 117) formed over the aluminum oxide (AlOx, N—AlOx), wherein the second silicon nitride layer (112) comprises a low silicon-hydrogen SiN material.
摘要翻译： 提供了氢屏障和制造方法，用于保护铁电电容器（CFE）在半导体器件（102）中的氢扩散，其中氮化的氧化铝（N-AlO x X）为 形成在铁电电容器（CFE）上，并且在氮化的氧化铝（N-AlO x N）上形成一个或多个氮化硅层（112,117）。 还提供了氢屏障，其中在铁电电容器（C FE）上形成氧化铝（AlO x N，N-AlO x x） ，其上形成有氧化铝（AlO x N，N-AlO x）上的两个或更多个氮化硅层（112,117），其中第二氮化硅层（112 ）包括低硅氢SiN材料。
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68.发明授权Versatile plasma processing system for producing oxidation resistant barriers 有权用于生产抗氧化屏障的多功能等离子体处理系统公开(公告)号：US06730616B2
公开(公告)日：2004-05-04
申请号：US10253338
申请日：2002-09-24
申请人： Scott R. Summerfelt
发明人： Scott R. Summerfelt
IPC分类号： H01L2131
CPC分类号： H01L21/76829 , H01L21/3144 , H01L21/76826 , H01L21/76831 , H01L21/76843 , H01L21/76849 , H01L21/76856 , H01L21/7687 , H01L28/55 , H01L28/60
摘要： A versatile system for forming diffusion barriers in semiconductor processing that simplifies device processing, utilizing existing production compounds and materials while resulting in uniform and proper device structuring, is disclosed, providing a system using a reactive plasma to selectively form diffusion barriers and provide selective oxidation.
摘要翻译： 公开了一种用于在半导体加工中形成扩散阻挡层的通用系统，其简化了器件加工，利用现有的生产化合物和材料，同时产生均匀且适当的器件结构，提供了使用反应性等离子体选择性地形成扩散阻挡层并提供选择性氧化的系统。
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公开(公告)号：US06555431B1
公开(公告)日：2003-04-29
申请号：US09712774
申请日：2000-11-16
IPC分类号： H01L218242
CPC分类号： H01L27/10852 , H01L21/32136 , H01L21/32139 , H01L28/55 , H01L28/60
摘要： A method for etching a feature in a platinum layer 834 overlying a second material 818 without substantially etching the second material. The method includes the the steps of: forming an adhesion-promoting layer 824 between the platinum layer and the second material; forming a hardmask layer 829 over the platinum layer; patterning and etching the hardmask layer in accordance with desired dimensions of the feature; and etching portions of the platinum layer not covered by the hardmask layer 832, the etching stopping on the adhesion-promoting layer. In further embodiments the adhesion-promoting and hardmask layers are Ti—Al—N including at least 1% of aluminum.
摘要翻译： 一种用于蚀刻铂层834中覆盖第二材料818而不基本上蚀刻第二材料的特征的方法。 该方法包括以下步骤：在铂层和第二材料之间形成粘合促进层824; 在铂层上形成硬掩模层829; 根据特征的期望尺寸对硬掩模层进行图案化和蚀刻; 并且蚀刻未被硬掩模层832覆盖的铂层的部分，蚀刻停止在粘合促进层上。 在另外的实施方案中，粘合促进和硬掩模层是包括至少1％的铝的Ti-Al-N。
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公开(公告)号：US06432473B1
公开(公告)日：2002-08-13
申请号：US08458999
申请日：1995-06-01
IPC分类号： B05D512
CPC分类号： H01L27/11502 , H01G4/1227 , H01L21/02197 , H01L21/31691
摘要： The invention described is a method of forming an improved dielectric material by adding lead to an original perovskite material having an original critical grain size to form a lead enhanced perovskite material, then forming a layer of the lead enhanced perovskite material having an average grain size less than the original critical grain size whereby the dielectric constant of the layer is substantially greater than the dielectric constant of the original perovskite material with an average grain size similar to the average grain size of the layer. The critical grain size, as used herein, means the largest grain size such that the dielectric constant starts to rapidly decrease with decreasing grain sizes. Preferably, the lead enhanced perovskite material is further doped with one or more acceptor dopants whereby the resistivity is substantially increased and/or the loss tangent is substantially decreased. Preferably, the original perovskite material has a chemical composition ABO3, where A is one or more monovalent, divalent or trivalent elements, and B is one or more pentavalent, tetravalent, trivalent or divalent elements.
摘要翻译： 本发明描述了一种通过将铅添加到具有原始临界晶粒尺寸的原始钙钛矿材料以形成铅增强的钙钛矿材料形成改进的介电材料的方法，然后形成平均晶粒尺寸较小的铅增强的钙钛矿材料层 比原始的临界晶粒大小，由此该层的介电常数基本上大于原始钙钛矿材料的介电常数，平均晶粒尺寸与层的平均晶粒尺寸相似。 如本文所用，临界晶粒尺寸是指最大的晶粒尺寸，使得随着晶粒尺寸的减小，介电常数开始迅速降低。 优选地，铅增强的钙钛矿材料进一步掺杂有一种或多种受体掺杂剂，由此电阻率显着增加和/或损耗角正切减小。 优选地，原始钙钛矿材料具有化学组成ABO 3，其中A是一个或多个一价，二价或三价元素，B是一种或多种五价，四价，三价或二价元素。
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