公开(公告)号：US10388796B2

公开(公告)日：2019-08-20

申请号：US15831763

申请日：2017-12-05

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei Yamazaki ,  Yuta Endo ,  Yoshiaki Oikawa

IPC: H01L29/786 ,  H01L29/51 ,  H01L21/02 ,  H01L29/66 ,  H01L29/778 ,  H01L29/24

Abstract: A semiconductor device with favorable electrical characteristics is provided. The semiconductor device includes a first conductor over a substrate; a first insulator over the first conductor; an oxide over the first insulator; a second insulator over the oxide; a second conductor over the second insulator; a third insulator over the second conductor; a fourth insulator in contact with a side surface of the second insulator, a side surface of the second conductor, and a side surface of the third insulator; and a fifth insulator in contact with the oxide, the first insulator, and the fourth insulator. The first insulator and the fifth insulator are in contact with each other in a region on the periphery of the side of the oxide. The oxide includes a first region where a channel is formed; a second region adjacent to the first region; a third region adjacent to the second region; and a fourth region adjacent to the third region. The first region has higher resistance than the second region, the third region, and the fourth region and overlaps with the second conductor. The second region has higher resistance than the third region and the fourth region and overlaps with the second conductor. The third region has higher resistance than the fourth region and overlaps with the fourth insulator.

公开(公告)号：US10256348B2

公开(公告)日：2019-04-09

申请号：US15903097

申请日：2018-02-23

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Yuta Endo ,  Hideomi Suzawa ,  Kazuya Hanaoka ,  Shinya Sasagawa ,  Satoru Okamoto

IPC: H01L29/40 ,  H01L29/786 ,  H01L27/12 ,  H01L27/146 ,  H01L29/423 ,  H01L29/49 ,  H01L29/66

Abstract: A semiconductor device in which parasitic capacitance is reduced is provided. A first oxide insulating layer and a first oxide semiconductor layer are sequentially formed over a first insulating layer. A first conductive layer is formed over the first oxide semiconductor layer and etched to form a second conductive layer. The first oxide insulating layer and the first oxide semiconductor layer are etched with the second conductive layer as a mask to form a second oxide insulating layer and a second oxide semiconductor layer. A planarized insulating layer is formed over the first insulating layer and the second conductive layer. A second insulating layer, a source electrode layer, and a drain electrode layer are formed by etching the planarized insulating layer and the second conductive layer. A third oxide insulating layer, a gate insulating layer, and a gate electrode layer are formed over the second oxide semiconductor layer.

公开(公告)号：US09905657B2

公开(公告)日：2018-02-27

申请号：US15408719

申请日：2017-01-18

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Yuta Endo ,  Hideomi Suzawa ,  Kazuya Hanaoka ,  Shinya Sasagawa ,  Satoru Okamoto

IPC: H01L29/40 ,  H01L29/786 ,  H01L29/66 ,  H01L29/423 ,  H01L29/49 ,  H01L27/12 ,  H01L27/146

CPC classification number: H01L29/78696 ,  H01L27/1225 ,  H01L27/14616 ,  H01L29/401 ,  H01L29/42384 ,  H01L29/4908 ,  H01L29/66969 ,  H01L29/78693 ,  H01L2029/42388

Abstract: A semiconductor device in which parasitic capacitance is reduced is provided. A first oxide insulating layer and a first oxide semiconductor layer are sequentially formed over a first insulating layer. A first conductive layer is formed over the first oxide semiconductor layer and etched to form a second conductive layer. The first oxide insulating layer and the first oxide semiconductor layer are etched with the second conductive layer as a mask to form a second oxide insulating layer and a second oxide semiconductor layer. A planarized insulating layer is formed over the first insulating layer and the second conductive layer. A second insulating layer, a source electrode layer, and a drain electrode layer are formed by etching the planarized insulating layer and the second conductive layer. A third oxide insulating layer, a gate insulating layer, and a gate electrode layer are formed over the second oxide semiconductor layer.

公开(公告)号：US09853165B2

公开(公告)日：2017-12-26

申请号：US14853542

申请日：2015-09-14

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shinya Sasagawa ,  Akihisa Shimomura ,  Katsuaki Tochibayashi ,  Yuta Endo ,  Shunpei Yamazaki

IPC: H01L29/786 ,  H01L21/311 ,  H01L21/3213 ,  H01L27/12

CPC classification number: H01L29/7869 ,  H01L21/31116 ,  H01L21/31138 ,  H01L21/31144 ,  H01L21/32136 ,  H01L21/32139 ,  H01L27/1225 ,  H01L29/78648

Abstract: A method for manufacturing a semiconductor device, including the steps of forming a semiconductor over a substrate; forming a first conductor over the semiconductor; forming a first insulator over the first conductor; forming a resist over the first insulator; performing light exposure and development on the resist to make a second region and a third region remain and expose part of the first insulator; applying a bias in a direction perpendicular to a top surface of the substrate and generating plasma using a gas containing carbon and halogen; and depositing and etching an organic substance with the plasma. The etching rate of the organic substance is higher than the deposition rate of the organic substance in an exposed part of the first insulator, and the deposition rate of the organic substance is higher than the etching rate of the organic substance in a side surface of the second region.

公开(公告)号：US09673305B2

公开(公告)日：2017-06-06

申请号：US14448015

申请日：2014-07-31

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Yuta Endo ,  Toshinari Sasaki ,  Kosei Noda

IPC: H01L29/66 ,  H01L29/51 ,  H01L29/423 ,  H01L21/477 ,  H01L21/425 ,  H01L29/786

CPC classification number: H01L29/66969 ,  H01L21/02 ,  H01L21/02112 ,  H01L21/02403 ,  H01L21/28 ,  H01L21/425 ,  H01L21/477 ,  H01L29/42384 ,  H01L29/518 ,  H01L29/78618 ,  H01L29/7869

Abstract: A semiconductor device is manufactured using a transistor in which an oxide semiconductor is included in a channel region and variation in electric characteristics due to a short-channel effect is less likely to be caused. The semiconductor device includes an oxide semiconductor film having a pair of oxynitride semiconductor regions including nitrogen and an oxide semiconductor region sandwiched between the pair of oxynitride semiconductor regions, a gate insulating film, and a gate electrode provided over the oxide semiconductor region with the gate insulating film positioned therebetween. Here, the pair of oxynitride semiconductor regions serves as a source region and a drain region of the transistor, and the oxide semiconductor region serves as the channel region of the transistor.

公开(公告)号：US09634149B2

公开(公告)日：2017-04-25

申请号：US14451854

申请日：2014-08-05

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Yuta Endo ,  Kosei Noda ,  Yuichi Sato

IPC: H01L29/786 ,  H01L21/336 ,  H01L29/49 ,  H01L21/02 ,  H01L21/3115 ,  H01L21/461 ,  H01L29/66

CPC classification number: H01L21/02554 ,  H01L21/02565 ,  H01L21/02576 ,  H01L21/02579 ,  H01L21/31155 ,  H01L21/461 ,  H01L21/823437 ,  H01L21/823857 ,  H01L29/0653 ,  H01L29/4908 ,  H01L29/4933 ,  H01L29/6659 ,  H01L29/66969 ,  H01L29/78603 ,  H01L29/78606 ,  H01L29/7869 ,  H01L29/78696

Abstract: A transistor that is formed using an oxide semiconductor film is provided. A transistor that is formed using an oxide semiconductor film with reduced oxygen vacancies is provided. A transistor having excellent electrical characteristics is provided. A semiconductor device includes a first insulating film, a first oxide semiconductor film, a gate insulating film, and a gate electrode. The first insulating film includes a first region and a second region. The first region is a region that transmits less oxygen than the second region does. The first oxide semiconductor film is provided at least over the second region.

公开(公告)号：US09577108B2

公开(公告)日：2017-02-21

申请号：US14281031

申请日：2014-05-19

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Yuta Endo ,  Toshinari Sasaki ,  Kosei Noda ,  Mizuho Sato

IPC: H01L21/02 ,  H01L29/786 ,  H01L27/12

CPC classification number: H01L29/7869 ,  H01L27/1225 ,  H01L29/78603 ,  H01L29/78606

Abstract: Disclosed is a semiconductor device with a transistor in which an oxide semiconductor is used. An insulating layer on a back channel side of the oxide semiconductor layer has capacitance of lower than or equal to 2×10−4 F/m2. For example, in the case of a top-gate transistor, a base insulating layer has capacitance of lower than or equal to 2×10−4 F/m2, whereby the adverse effect of an interface state between the substrate and the base insulating layer can be reduced. Thus, a semiconductor device where fluctuation in electrical characteristics is small and reliability is high can be manufactured.

Abstract translation: 公开了具有使用氧化物半导体的晶体管的半导体器件。 氧化物半导体层的背面通道侧的绝缘层的电容为2×10 -4 F / m 2以下。 例如，在顶栅晶体管的情况下，基极绝缘层具有小于或等于2×10 -4 F / m 2的电容，由此衬底和基极绝缘层之间的界面态的不利影响 可以减少 因此，可以制造电特性波动小，可靠性高的半导体装置。

公开(公告)号：US09443988B2

公开(公告)日：2016-09-13

申请号：US14501965

申请日：2014-09-30

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Yuta Endo ,  Toshinari Sasaki ,  Kosei Noda ,  Mizuho Sato ,  Mitsuhiro Ichijo ,  Toshiya Endo

IPC: H01L29/10 ,  H01L29/786 ,  H01L29/49 ,  H01L29/24 ,  H01L29/51

CPC classification number: H01L29/7869 ,  H01L29/24 ,  H01L29/4908 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66969 ,  H01L29/78603 ,  H01L29/78606

Abstract: In a transistor having a top-gate structure in which a gate electrode layer overlaps with an oxide semiconductor layer which faints a channel region with a gate insulating layer interposed therebetween, when a large amount of hydrogen is contained in the insulating layer, hydrogen is diffused into the oxide semiconductor layer because the insulating layer is in contact with the oxide semiconductor layer; thus, electric characteristics of the transistor are degraded. An object is to provide a semiconductor device having favorable electric characteristics. An insulating layer in which the concentration of hydrogen is less than 6×1020 atoms/cm3 is used for the insulating layer being in contact with oxide semiconductor layer which forms the channel region. Using the insulating layer, diffusion of hydrogen can be prevented and a semiconductor device having favorable electric characteristics can be provided.

Abstract translation: 在具有栅极结构的晶体管中，栅电极层与其间插入有栅极绝缘层的沟道区域的氧化物半导体层重叠，当绝缘层中含有大量的氢时，氢扩散 由于绝缘层与氧化物半导体层接触，所以进入氧化物半导体层; 因此，晶体管的电特性降低。 本发明的目的是提供一种具有良好电特性的半导体器件。 与形成沟道区域的氧化物半导体层接触的绝缘层使用其氢浓度小于6×1020原子/ cm3的绝缘层。 使用绝缘层，可以防止氢的扩散，并且可以提供具有良好电特性的半导体器件。

公开(公告)号：US09318618B2

公开(公告)日：2016-04-19

申请号：US14580590

申请日：2014-12-23

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Yuta Endo ,  Kosei Noda

IPC: H01L29/786 ,  H01L27/088 ,  H01L29/16

CPC classification number: H01L29/7869 ,  H01L27/088 ,  H01L29/16 ,  H01L29/78648 ,  H01L29/78696

Abstract: To provide a transistor with stable electric characteristics, provide a transistor having a small current in a non-conductive state, provide a transistor having a large current in a conductive state, provide a semiconductor device including the transistor, or provide a durable semiconductor device, a semiconductor device includes a first insulator containing excess oxygen, a semiconductor over the first insulator, a second insulator over the semiconductor, and a conductor having a region overlapping with the semiconductor with the second insulator provided therebetween. A region containing boron or phosphorus is located between the first insulator and the semiconductor.

Abstract translation: 为了提供具有稳定电特性的晶体管，提供具有非导通状态的小电流的晶体管，提供具有导通状态的大电流的晶体管，提供包括晶体管的半导体器件，或提供耐用的半导体器件， 半导体器件包括含有过量氧的第一绝缘体，在第一绝缘体上的半导体，半导体上的第二绝缘体，以及具有与半导体重叠的区域的导体，其间设置有第二绝缘体。 含有硼或磷的区域位于第一绝缘体和半导体之间。

公开(公告)号：US09082864B2

公开(公告)日：2015-07-14

申请号：US14537232

申请日：2014-11-10

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Toshinari Sasaki ,  Kosei Noda ,  Yuta Endo

IPC: H01L29/10 ,  H01L29/12 ,  H01L29/786 ,  H01L29/24 ,  H01L29/04

CPC classification number: H01L29/78696 ,  H01L29/045 ,  H01L29/24 ,  H01L29/247 ,  H01L29/7869 ,  H01L29/78693

Abstract: A highly reliable semiconductor device is manufactured by giving stable electric characteristics to a transistor in which an oxide semiconductor film is used. A p-type oxide semiconductor material is contained in an n-type oxide semiconductor film, whereby carriers which are generated in the oxide semiconductor film without intention can be reduced. This is because electrons generated in the n-type oxide semiconductor film without intention are recombined with holes generated in the p-type oxide semiconductor material to disappear. Accordingly, it is possible to reduce carriers which are generated in the oxide semiconductor film without intention.

Abstract translation: 通过对使用氧化物半导体膜的晶体管赋予稳定的电特性来制造高可靠性的半导体器件。 p型氧化物半导体材料包含在n型氧化物半导体膜中，由此可以减少在氧化物半导体膜中产生的载流子。 这是因为在n型氧化物半导体膜中产生的电子没有意图与在p型氧化物半导体材料中产生的空穴重新组合而消失。 因此，可以无意地减少在氧化物半导体膜中产生的载流子。