公开(公告)号：US06303192B1

公开(公告)日：2001-10-16

申请号：US09121180

申请日：1998-07-22

Applicant: Rao V. Annapragada ,  Tekle M. Tafari ,  Subhas Bothra

Inventor： Rao V. Annapragada ,  Tekle M. Tafari ,  Subhas Bothra

IPC: C23C1416

CPC classification number: H01L21/02137 ,  C23C16/0272 ,  C23C16/505 ,  H01L21/02282 ,  H01L21/0234 ,  H01L21/02362 ,  H01L21/3105 ,  H01L21/31058 ,  H01L21/3122 ,  H01L21/316 ,  H01L21/76801 ,  H01L21/76826 ,  H01L21/76829 ,  H01L23/5222 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method for making a multi-layered integrated circuit structure, includes depositing a methyl compound spin on glass layer over a substrate. The spin on glass layer is treated by plasma-deposition to form a SiO2 skin on the methyl compound spin on glass layer and then treated again by plasma-deposition to form a cap layer which adheres to the SiO2 skin.

Abstract translation: 一种制造多层集成电路结构的方法，包括在衬底上沉积甲基化合物旋涂在玻璃层上。 通过等离子体沉积处理玻璃层上的旋涂，在玻璃层上的甲基化合物旋涂上形成SiO 2皮肤，然后通过等离子体沉积再次处理以形成粘附于SiO 2皮肤的盖层。

公开(公告)号：US06297557B1

公开(公告)日：2001-10-02

申请号：US09134070

申请日：1998-08-13

Applicant: Subhas Bothra

Inventor： Subhas Bothra

IPC: H01L2348

CPC classification number: H01L21/76876 ,  H01L21/76838 ,  H01L21/76843 ,  H01L21/76849 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/53223 ,  H01L2924/0002 ,  Y10S438/927 ,  H01L2924/00

Abstract: Disclosed is an aluminum filled via hole for use in a semiconductor interconnect structure. The aluminum filled via hole of the semiconductor interconnect structure includes a first patterned metallization layer lying over a first dielectric layer. A second dielectric layer overlying the first patterned metallization layer and the first dielectric layer. An aluminum filled via hole defined through the second dielectric layer and in contact with the first patterned metallization layer. The aluminum filled via hole has an electromigration barrier cap over a topmost portion of the aluminum filled via hole that is substantially level with the second dielectric layer. The electromigration barrier cap having a thickness of between about 500 angstroms and about 2,500 angstroms.

Abstract translation: 公开了一种用于半导体互连结构的铝填充通孔。 半导体互连结构的铝填充通孔包括位于第一介电层上的第一图案化金属化层。 覆盖第一图案化金属化层和第一介电层的第二电介质层。 通过第二介电层限定并与第一图案化金属化层接触的铝填充通孔。 铝填充的通孔在铝填充的通孔的最上部具有与第二介电层基本平齐的电迁移阻挡帽。 电迁移阻挡盖的厚度介于约500埃至约2500埃之间。

公开(公告)号：US06226782B1

公开(公告)日：2001-05-01

申请号：US09304886

申请日：1999-05-04

Applicant: Edward D. Nowak ,  Subhas Bothra

Inventor： Edward D. Nowak ,  Subhas Bothra

IPC: G06F1700

CPC classification number: H01L23/528 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Disclosed is an apparatus for generating mask data suitable to produce a support pillar mask used in air dielectric interconnect structures. The apparatus includes a mask data scanner configured to select features having an interconnect dimension from a first mask. The features having the interconnect dimension being defined to electrically interconnect devices distributed on a substrate. The apparatus further includes a mask data comparing engine for comparing mask data associated with an intermediate support pattern and mask data associated with the features having the interconnect dimension selected by the mask data scanner. The comparing being configured to identify a mask area where the intermediate support pattern and the features having the interconnect dimension overlap. Preferably, the identified mask area defines the location of a plurality of pillars.

Abstract translation: 公开了一种用于产生适于产生用于空气电介质互连结构中的支撑柱掩模的掩模数据的装置。 该装置包括掩模数据扫描器，其被配置为从第一掩模中选择具有互连尺寸的特征。 具有互连尺寸的特征被限定为电连接分布在衬底上的器件。 该装置还包括掩模数据比较引擎，用于比较与中间支持模式相关联的掩模数据和与由掩模数据扫描器选择的具有互连尺寸的特征相关联的掩模数据。 比较被配置为识别中间支撑图案和具有互连尺寸的特征重叠的掩模区域。 优选地，所识别的掩模区域限定多个柱的位置。

公开(公告)号：US06214734B1

公开(公告)日：2001-04-10

申请号：US09197377

申请日：1998-11-20

Applicant: Subhas Bothra ,  Milind G. Weling

Inventor： Subhas Bothra ,  Milind G. Weling

IPC: H01L21302

CPC classification number: B24B37/013 ,  B24B37/042 ,  H01L21/31053 ,  Y10S438/959 ,  Y10T428/24917

Abstract: A method of using films having optimized optical properties for chemical mechanical polishing (CMP) endpoint detection. Specifically, one embodiment of the present invention includes a method for improving chemical mechanical polishing endpoint detection. The method comprises the step of depositing a dielectric layer over a reflectance stop layer. The reflectance stop layer is disposed above a component that is disposed on a semiconductor wafer. During a determination of the thickness of the dielectric layer using a reflected signal of light, the reflectance stop layer substantially reduces any light from reflecting off of the component. Therefore, the present invention provides a method and system that provides more accurate endpoint detection during a CMP process of semiconductor wafers. As a result of the present invention, an operator of a CMP machine knows precisely when to stop a CMP process of a semiconductor wafer. Furthermore, the present invention enables the operator of the CMP machine to know within a certain accuracy the film (e.g., dielectric layer) thickness remaining after the CMP process of the semiconductor wafer. Moreover, the present invention essentially eliminates excessive chemical mechanical polishing of the semiconductor wafer. As such, not as much dielectric material needs to be deposited on the wafer in order to compensate for excessive chemical mechanical polishing of the semiconductor wafer. Therefore, the present invention is able to reduce fabrication costs of semiconductor wafers.

Abstract translation: 使用具有优化的光学性质的膜用于化学机械抛光（CMP）端点检测的方法。 具体地，本发明的一个实施方案包括用于改进化学机械抛光终点检测的方法。 该方法包括在反射停止层上沉积介电层的步骤。 反射阻挡层设置在配置在半导体晶片上的部件的上方。 在使用光的反射信号确定介电层的厚度期间，反射率停止层基本上减少了从组件反射的任何光。 因此，本发明提供了一种在半导体晶片的CMP工艺期间提供更准确的端点检测的方法和系统。 作为本发明的结果，CMP机器的操作者精确地知道何时停止半导体晶片的CMP工艺。 此外，本发明使得CMP机器的操作者能够在半导体晶片的CMP处理之后以一定的精度了解剩余的膜（例如介电层）的厚度。 此外，本发明基本上消除了半导体晶片的过度的化学机械抛光。 因此，为了补偿半导体晶片的过度的化学机械抛光，不需要在晶片上沉积太多的介电材料。 因此，本发明能够降低半导体晶片的制造成本。

公开(公告)号：US06191481B1

公开(公告)日：2001-02-20

申请号：US09215099

申请日：1998-12-18

Applicant: Subhas Bothra ,  Stephen L. Skala ,  Dipu Pramanik

Inventor： Subhas Bothra ,  Stephen L. Skala ,  Dipu Pramanik

IPC: H01L2348

CPC classification number: H01L23/528 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Disclosed is a semiconductor integrated circuit device having a plurality of metallization levels of patterned metallization lines that are resistant to electromigration voiding, and methods for making the electromigration void resistant metallization lines. The semiconductor integrated circuit device includes a metallization line having a first end and a second end. Oxide feature regions are defined in the metallization line, and the oxide feature regions are arranged along the metallization line between the first end and the second end. Each one of the oxide feature regions are configured to be separated from a previous oxide feature region by about a Blech length or less, and each of the oxide feature regions are configured to define a region of increased metallization atom concentration and a corresponding increased back-flow force. The oxide feature regions therefore define a composite metallization interconnect line, which is well configured to retard electromigration voiding.

Abstract translation: 本发明公开了一种半导体集成电路器件，其具有耐电迁移排空的图案化金属化线的多个金属化水平，以及用于制造电迁移空隙的金属化线的方法。 半导体集成电路器件包括具有第一端和第二端的金属化线。 氧化物特征区域被限定在金属化线中，并且氧化物特征区域沿着第一端和第二端之间的金属化线布置。 氧化物特征区域中的每一个被配置为与先前的氧化物特征区域分开大约Blech长度或更小，并且每个氧化物特征区域被配置为限定增加的金属化原子浓度的区域和相应的增加的反向 流动力。 因此，氧化物特征区域限定复合金属化互连线，其良好构造以延迟电迁移排空。

公开(公告)号：US6153531A

公开(公告)日：2000-11-28

申请号：US995679

申请日：1997-12-22

Applicant: Subhas Bothra ,  Jay Patel

Inventor： Subhas Bothra ,  Jay Patel

IPC: H01L21/768 ,  H01L21/302

CPC classification number: H01L21/76888

Abstract: Disclosed is a method for fabricating reliable interconnect structures on a semiconductor substrate that has at least a first dielectric layer, a first patterned metallization layer, a second dielectric layer over the first patterned metallization layer, and a plurality of tungsten plugs formed in the second dielectric layer. The method includes patterning a second metallization layer that overlies the second dielectric layer and the plurality of tungsten plugs, such that the patterning leaves at least one of the plurality of tungsten plugs not completely covered by the second metallization layer. Submersing the semiconductor substrate into a dilute nitric acid solution until a passivating tungsten oxide is formed over a portion of the at least one of the plurality of tungsten plugs that is not completely covered by the second metallization layer. The method further includes submersing the semiconductor substrate into a basic cleaning solution, and the passivating tungsten oxide is configured to prevent the at least one of the plurality of tungsten plugs from eroding in the basic cleaning solution. Preferably, the dilute nitric acid solution is adjusted to have a pH level of between about 1.5 and about 3 so that the passivating tungsten oxide becomes insoluble.

Abstract translation: 公开了一种用于在半导体衬底上制造可靠的互连结构的方法，其具有至少第一介电层，第一图案化金属化层，在第一图案化金属化层上的第二电介质层，以及形成在第二电介质中的多个钨塞 层。 该方法包括图案化覆盖第二介电层和多个钨塞的第二金属化层，使得图案化使多个钨插塞中的至少一个未被第二金属化层完全覆盖。 将半导体衬底浸入稀硝酸溶液中，直到在多个钨插塞中的至少一个钨塞未被第二金属化层完全覆盖的部分上形成钝化氧化钨。 该方法还包括将半导体衬底浸入基本清洁溶液中，并且钝化氧化钨被配置为防止多个钨塞中的至少一个在基本清洁溶液中侵蚀。 优选地，将稀硝酸溶液调节至pH值在约1.5至约3之间，以使钝化氧化钨变得不溶。

公开(公告)号：US6133635A

公开(公告)日：2000-10-17

申请号：US884795

申请日：1997-06-30

Applicant: Subhas Bothra ,  Jacob Haskell

Inventor： Subhas Bothra ,  Jacob Haskell

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/532 ,  H01L23/48

CPC classification number: H01L21/76885 ,  H01L21/7682 ,  H01L21/76897 ,  H01L23/5226 ,  H01L23/5329 ,  H01L2924/0002

Abstract: Disclosed is a process for making a self-aligning conductive via structure in a semiconductor device. The process includes forming a first interconnect metallization layer over an oxide layer. Forming an etch stop layer over the first interconnect metallization layer. Forming a conductive via metallization layer over the etch stop layer. Forming a hard mask layer over the conductive via metallization layer. The process further includes producing a conductive via and an interconnect line, where the conductive via is formed from a portion of the conductive via metallization layer, and the interconnect line is formed from a portion of the first interconnect metallization layer. The conductive via is substantially aligned with the underlying interconnect line.

Abstract translation: 公开了一种在半导体器件中制造自对准导电通孔结构的方法。 该工艺包括在氧化物层上形成第一互连金属化层。 在第一互连金属化层上形成蚀刻停止层。 在蚀刻停止层上形成导电通孔金属化层。 在导电通孔金属化层上形成硬掩模层。 该方法还包括制造导电通孔和互连线，其中导电通孔由导电通孔金属化层的一部分形成，并且互连线由第一互连金属化层的一部分形成。 导电通孔基本上与下面的互连线对准。

公开(公告)号：US6127811A

公开(公告)日：2000-10-03

申请号：US228707

申请日：1999-01-12

Applicant: Jayarama N. Shenoy ,  Subhas Bothra

Inventor： Jayarama N. Shenoy ,  Subhas Bothra

IPC: B81C99/00 ,  H01G5/013 ,  H01G5/40 ,  H02N1/08 ,  H01M10/46

CPC classification number: H01G5/0138 ,  B81C99/00 ,  H01G5/40 ,  H02N1/08

Abstract: The present invention includes a micro-electromechanical system and voltage shifter, method of synchronizing an electronic system and a micromechanical system of a micro-electromechanical system. According to one aspect, the present invention provides a micro-electromechanical system voltage shifter including at least one node; a capacitor including plural opposing conductive plates; a micromechanical system configured to vary the capacitance of the capacitor; an electrical system configured to selectively couple the capacitor and the at least one node; and a mixer configured to output a product signal to synchronize the micromechanical system and the electrical system. Another aspect provides a method of synchronizing an electronic system and a micromechanical system of a micro-electromechanical system voltage shifter, the method including providing a capacitor and at least one node; varying the capacitance of the capacitor using a micromechanical system; selectively coupling the capacitor with the at least one node using an electrical system to one of charge the capacitor and provide sampling of the voltage of the capacitor; and synchronizing the electrical system and the micromechanical system.

Abstract translation: 本发明包括微机电系统和电压转换器，电子系统的同步方法和微机电系统的微机械系统。 根据一个方面，本发明提供了一种包括至少一个节点的微机电系统电压转换器; 电容器，包括多个相对的导电板; 配置为改变电容器的电容的微机械系统; 电系统，被配置为选择性地耦合所述电容器和所述至少一个节点; 以及配置成输出产品信号以使微机械系统和电气系统同步的混合器。 另一方面提供了一种同步电子系统和微机电系统电压转换器的微机械系统的方法，该方法包括提供电容器和至少一个节点; 使用微机械系统改变电容器的电容; 使用电气系统将所述电容器与所述至少一个节点选择性耦合到对所述电容器进行充电之一并且提供所述电容器的电压的采样; 并使电气系统和微机械系统同步。

公开(公告)号：US6093658A

公开(公告)日：2000-07-25

申请号：US995651

申请日：1997-12-22

Applicant: Subhas Bothra ,  Harlan Lee Sur, Jr. ,  Victor C. Liang

Inventor： Subhas Bothra ,  Harlan Lee Sur, Jr. ,  Victor C. Liang

IPC: H01L21/02 ,  H01L21/311 ,  H01L21/3205 ,  H01L21/3213 ,  H01L21/768 ,  H01L23/522 ,  H01L21/302

CPC classification number: H01L21/02071 ,  H01L21/32051 ,  H01L21/76838 ,  H01L23/5226 ,  H01L21/31133 ,  H01L2924/0002

Abstract: Disclosed is a method for making reliable interconnect structures on a semiconductor wafer having a first dielectric layer. The method includes plasma patterning a first metallization layer over the first dielectric layer. Forming a second dielectric layer over the first metallization layer and the first dielectric layer. Forming a plurality of tungsten plugs in the second dielectric layer, such that each of the plurality of tungsten plugs are in electrical contact with the first metallization layer. Plasma patterning a second metallization layer over the second dielectric layer and the plurality of tungsten plugs, such that at least a gap over at least one of the tungsten plugs is not covered by the second metallization layer and a positive charge is built-up on at least part of the second metallization layer. The method further includes exposing the semiconductor wafer to an electron dose that is configured to neutralize the positive charge that is built-up on the at least part of the second metallization layer. The neutralizing is thus configured to substantially prevent tungsten plug erosion.

Abstract translation: 公开了一种在具有第一介电层的半导体晶片上制造可靠的互连结构的方法。 该方法包括在第一介电层上的等离子体图案化第一金属化层。 在第一金属化层和第一介电层上形成第二电介质层。 在第二电介质层中形成多个钨塞，使得多个钨塞中的每一个与第一金属化层电接触。 等离子体在第二电介质层和多个钨插塞上构图第二金属化层，使得至少一个钨插塞上的至少一个间隙不被第二金属化层覆盖，并且正电荷在 第二金属化层的最少部分。 该方法还包括将半导体晶片暴露于被配置为中和在第二金属化层的至少部分上积累的正电荷的电子剂量。 因此，中和被构造成基本上防止钨插塞侵蚀。

公开(公告)号：US6080661A

公开(公告)日：2000-06-27

申请号：US87441

申请日：1998-05-29

Applicant: Subhas Bothra

Inventor： Subhas Bothra

IPC: H01L21/60 ,  H01L21/4763

CPC classification number: H01L21/76897

Abstract: Disclosed are methods for making reliable conductive vias in semiconductor devices that are fabricated over a semiconductor wafer. The semiconductor device includes a plurality of transistor devices having diffusion regions and polysilicon gate electrodes, and an oxide material that covers a top surface of the polysilicon gate electrodes of the transistor devices. A silicon nitride layer is also disposed over the semiconductor devices and a dielectric layer is disposed over the silicon nitride layer. The method includes depositing a silicon nitride layer over the dielectric layer, and etching nitride windows in the silicon nitride layer to expose the dielectric layer where conductive contacts to selected polysilicon gate electrodes are desired. The method then includes pattering a photoresist mask over the silicon nitride layer. The photoresist mask is configured to have a plurality of windows defining all contacts to both selected ones of the diffusion regions and selected ones of the polysilicon gate electrodes, and some of the plurality of windows are defined over the nitride windows. Furthermore, the method includes performing a series of dielectric and silicon nitride etch operations to substantially simultaneously form via holes down to selected polysilicon gate electrodes and selected diffusion regions. Once the via holes are etched, a suitable conductive contact fill process may be performed.

Abstract translation: 公开了在半导体晶片上制造的半导体器件中制造可靠的导电通孔的方法。 半导体器件包括具有扩散区域和多晶硅栅电极的多个晶体管器件和覆盖晶体管器件的多晶硅栅电极的顶表面的氧化物材料。 氮化硅层也设置在半导体器件上方，并且介电层设置在氮化硅层上。 该方法包括在电介质层上沉积氮化硅层，以及蚀刻氮化硅层中的氮化物窗口以暴露需要与所选择的多晶硅栅电极的导电接触的电介质层。 该方法然后包括在氮化硅层上图案化光致抗蚀剂掩模。 光致抗蚀剂掩模被配置为具有多个窗口，其限定了所选择的扩散区域中的所选择的一个以及多晶硅栅极电极中的所选择的多个栅电极的所有触点，并且多个窗口中的一些限定在氮化物窗口上。 此外，该方法包括执行一系列电介质和氮化硅蚀刻操作，以基本上同时形成向下选定的多晶硅栅电极和选定扩散区的通孔。 一旦通孔被蚀刻，就可以执行合适的导电接触填充过程。