公开(公告)号：US5910453A

公开(公告)日：1999-06-08

申请号：US584941

申请日：1996-01-16

申请人： Subhash Gupta ,  Mutya Vicente

发明人： Subhash Gupta ,  Mutya Vicente

IPC分类号： H01L21/027 ,  H01L21/308 ,  H01L21/311 ,  H01L21/312 ,  H01L21/302

CPC分类号： H01L21/0276 ,  H01L21/3081 ,  H01L21/31144 ,  H01L21/31116 ,  H01L21/312

摘要： An etching process for DUV photolithography is provided for etching a layer of anti-reflection coating (ARC) comprising spin-on organic ARC material which is formed beneath a layer of photoresist. After patterning the layer of photoresist, the layer of ARC is etched by employing a mixture of oxygen plasma, nitrogen plasma, and at least one inert gas. Anisotropic etching of the layer of ARC is provided with the process of the present invention. In comparison with prior art etching processes for etching a layer of ARC, the process of the present invention provides a favorable etch rate with improved selectivity over the etching of the layer of photoresist. The layer of ARC is etched without causing lateral erosion of the layer of photoresist. Faceting of the top edges of the corners of the layer of photoresist is also minimized. The profile of the layer of photoresist is essentially maintained thereby enabling for critical dimension fidelity. The process of the present invention is residue-free, and provides favorable selectivity for etching the layer of ARC over most underlying materials conventionally used in integrated circuit structures. The layer of ARC can also be etched by employing a mixture of nitrogen plasma and inert gas. Employing a mixture of nitrogen plasma and inert gas, without oxygen plasma, provides a reduced etch rate.

摘要翻译： 提供了用于DUV光刻的蚀刻工艺，用于蚀刻包含形成在光致抗蚀剂层下面的旋涂有机ARC材料的抗反射涂层（ARC）层。 在图案化光致抗蚀剂层之后，通过使用氧等离子体，氮等离子体和至少一种惰性气体的混合物蚀刻ARC层。 本发明的方法提供了ARC层的各向异性蚀刻。 与用于蚀刻ARC层的现有技术的蚀刻工艺相比，本发明的方法提供了对蚀刻光致抗蚀剂层的优选蚀刻速率。 蚀刻ARC层，不会引起光致抗蚀剂层的横向侵蚀。 光致抗蚀剂层的角部的顶部边缘的表面也被最小化。 基本上保持光致抗蚀剂层的轮廓，从而能够实现临界尺寸保真度。 本发明的方法是无残留的，并且为通常用于集成电路结构的大多数底层材料提供了对ARC层蚀刻的良好选择性。 也可以通过使用氮等离子体和惰性气体的混合物来蚀刻ARC层。 使用无等离子体的氮等离子体和惰性气体的混合物提供降低的蚀刻速率。

公开(公告)号：US5770519A

公开(公告)日：1998-06-23

申请号：US464305

申请日：1995-06-05

申请人： Richard K. Klein ,  Darrell Erb ,  Steven Avanzino ,  Robin Cheung ,  Scott Luning ,  Bryan Tracy ,  Subhash Gupta ,  Ming-Ren Lin

发明人： Richard K. Klein ,  Darrell Erb ,  Steven Avanzino ,  Robin Cheung ,  Scott Luning ,  Bryan Tracy ,  Subhash Gupta ,  Ming-Ren Lin

IPC分类号： H01L21/768 ,  H01L23/522 ,  H01L23/532 ,  H01L21/4763 ,  H01L21/44

CPC分类号： H01L21/76831 ,  H01L21/76805 ,  H01L21/76843 ,  H01L21/76844 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/53223 ,  H01L2924/0002

摘要： A multilayer semiconductor structure includes a conductive via. The conductive via includes a reservoir of metal having a high resistance to electromigration. The reservoir is made from a conformal layer of copper, or gold deposited over the via to form a copper, or gold plug located in the via. A barrier layer is provided between the reservoir and an insulating layer to prevent the reservoir from diffusing into the insulating layer. The barrier layer and reservoir may be deposited by sputtering, collimated sputtering, chemical vapor deposition (CVD), dipping, evaporating, or by other means. The barrier layer and reservoir may be etched by anisotropic dry etching, plasma-assisted etching, or other layer removal techniques.

摘要翻译： 多层半导体结构包括导电通孔。 导电通孔包括具有高抗电迁移性的金属储存器。 储存器由铜的共形层或沉积在通孔上的金形成，以形成位于通孔中的铜或金塞。 在储存器和绝缘层之间设置阻挡层，以防止储存器扩散到绝缘层中。 可以通过溅射，准直溅射，化学气相沉积（CVD），浸渍，蒸发或其它方式沉积阻挡层和储层。 可以通过各向异性干蚀刻，等离子体辅助蚀刻或其它层去除技术来蚀刻阻挡层和储存器。

公开(公告)号：US5686354A

公开(公告)日：1997-11-11

申请号：US478324

申请日：1995-06-07

申请人： Steven Avanzino ,  Subhash Gupta ,  Rich Klein ,  Scott D. Luning ,  Ming-Ren Lin

发明人： Steven Avanzino ,  Subhash Gupta ,  Rich Klein ,  Scott D. Luning ,  Ming-Ren Lin

IPC分类号： H01L21/768 ,  H01L21/28

CPC分类号： H01L21/76831 ,  H01L21/76807

摘要： A dual damascene method of fabricating an interconnection level of conductive lines and connecting vias separated by insulation for integrated circuits and substrate carriers for semiconductor devices using a thin protective via mask to form the via openings. A conductive line mask pattern is used to form conductive line openings in an insulating layer. Next, a thin protective layer of conformal material is deposited in the conducive line opening. The protective layer and the insulating layer each have etch resistance to others etchant. Using a via mask pattern, openings are etching the protective layer with the insulating layer serving as and etch stop. Next via openings are etched in the insulating material using the openings in the thin protective layer as the etch mask. If the protective layer is a conductive material, it is removed from the surface of the insulating layer either before or after the conductive line and via openings are filled with a conductive material. If the protective material is an insulating material, it is entirely removed before filling the conductive line and via openings conductive material.

摘要翻译： 一种双镶嵌方法，用于制造导线的互连级别并且连接用于集成电路的绝缘和用于半导体器件的衬底载体的通孔，其使用薄的保护性通孔掩模形成通孔。 导电线掩模图案用于在绝缘层中形成导电线路开口。 接下来，在导电线路开口中沉积有保形材料的薄保护层。 保护层和绝缘层各自具有对其它蚀刻剂的耐蚀刻性。 使用通孔掩模图案，开口蚀刻保护层，绝缘层用作蚀刻停止。 接下来通过开口被蚀刻在绝缘材料中，使用薄保护层中的开口作为蚀刻掩模。 如果保护层是导电材料，则在导电线之前或之后将其从绝缘层的表面去除，并且通孔开口填充有导电材料。 如果保护材料是绝缘材料，则在填充导电线和通孔开口导电材料之前将其完全去除。

公开(公告)号：US5319586A

公开(公告)日：1994-06-07

申请号：US18343

申请日：1993-02-16

申请人： Subhash Gupta ,  Ravi Mehrotra

发明人： Subhash Gupta ,  Ravi Mehrotra

IPC分类号： G06F17/12 ,  G06F17/16 ,  G06F15/32 ,  G06F7/00

CPC分类号： G06F17/12 ,  G06F17/16

摘要： An apparatus and method for performing matrix calculations is provided. The apparatus comprises a computer system having a linearly connected array of processors. Each processor has three inputs, two of which receive data along the linear array. The processors are configured to perform certain multiply-add operations. The methods permit speeded up solution of systems of linear equations and matrix inversion. The methods involve manipulating the matrices and the unknown vector values such that the problem can be solved using vector orthogonalization techniques.

摘要翻译： 提供了一种用于执行矩阵计算的装置和方法。 该装置包括具有线性连接的处理器阵列的计算机系统。 每个处理器有三个输入，其中两个输入沿线性阵列接收数据。 处理器被配置为执行某些乘法加法操作。 该方法允许加速线性方程组和矩阵反演系统的解。 该方法涉及操纵矩阵和未知向量值，使得可以使用向量正交化技术来解决问题。

公开(公告)号：US5198298A

公开(公告)日：1993-03-30

申请号：US426147

申请日：1989-10-24

申请人： Jacob D. Haskell ,  Subhash Gupta

发明人： Jacob D. Haskell ,  Subhash Gupta

IPC分类号： H01L21/3105 ,  H01L21/311 ,  H01L21/768

CPC分类号： H01L21/76801 ,  H01L21/31055 ,  H01L21/31116 ,  H01L21/76834 ,  Y10S438/97 ,  Y10T428/265 ,  Y10T428/31612 ,  Y10T428/31663

摘要： An etch stop player (22) for permitting distinguishing between two similar layers (20, 24), such as two oxide layers, during etching is provided. The etch stop layer comprises a silicon-oxyhalide polymer, preferably a silicon-oxyfluoride polymer. Use of the polymer as an etch stop layer permits closer placement of metal conductor surfaces (12, 12') and contacts (14').

摘要翻译： 提供了用于允许在蚀刻期间区分两个相似层（20,24）（例如两个氧化物层）的蚀刻停止播放器（22）。 蚀刻停止层包括硅 - 卤氧化物聚合物，优选硅 - 氟氧化物聚合物。 使用聚合物作为蚀刻停止层允许金属导体表面（12,12'）和触点（14'）的更靠近的放置。

公开(公告)号：US4992134A

公开(公告)日：1991-02-12

申请号：US436282

申请日：1989-11-14

申请人： Subhash Gupta ,  Kashmir Sahota

发明人： Subhash Gupta ,  Kashmir Sahota

IPC分类号： H01L21/302 ,  H01L21/3065 ,  H01L21/3213 ,  H01L21/8238 ,  H01L27/092

CPC分类号： H01L21/3065 ,  H01L21/32137

摘要： A plasma etching process is provided which etches n-type, p-type, and intrinsic polysilicon on the same wafer at substantially the same rate. Native oxide is first removed by etching in a conventional oxide etchant, such as SiCl.sub.4 /Cl.sub.2, BCl.sub.3 /Cl.sub.2, CCl.sub.4, other mixtures of fluorinated or chlorinated gases, and mixtures of Freon-based gases. The polysilicon is then etched in an etchant comprising at least about 75% hydrogen and the balance a halogen-containing fluid, such as chloride. The silicon etchant etches at a rate of about 300 to 500 .ANG. for a batch of 10 wafers, depending on hydrogen concentration, power, flow rate of gas mixture, and gas pressure.

公开(公告)号：US06821888B2

公开(公告)日：2004-11-23

申请号：US10076244

申请日：2002-02-13

申请人： Yakub Aliyu ,  Simon Chooi ,  Meisheng Zhou ,  John Sudijono ,  Subhash Gupta ,  Sudipto Ranendra Roy

发明人： Yakub Aliyu ,  Simon Chooi ,  Meisheng Zhou ,  John Sudijono ,  Subhash Gupta ,  Sudipto Ranendra Roy

IPC分类号： H01L2144

CPC分类号： H01L24/13 ,  H01L24/11 ,  H01L24/81 ,  H01L2224/05001 ,  H01L2224/05023 ,  H01L2224/0508 ,  H01L2224/05568 ,  H01L2224/1147 ,  H01L2224/1308 ,  H01L2224/13083 ,  H01L2224/13147 ,  H01L2224/1319 ,  H01L2224/1329 ,  H01L2224/133 ,  H01L2224/81801 ,  H01L2924/00013 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01078 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15747 ,  H01L2924/00014 ,  H01L2224/13099 ,  H01L2924/00

摘要： A semiconductor chip having an exposed metal terminating pad thereover, and a separate substrate having a corresponding exposed metal bump thereover are provided. A conducting polymer plug is formed over the exposed metal terminating pad. A conforming interface layer is formed over the conducting polymer plug. The conducting polymer plug of the semiconductor chip is aligned with the corresponding metal bump. The conforming interface layer over the conducting polymer plug is mated with the corresponding metal bump. The conforming interface layer is thermally decomposed, adhering and permanently attaching the conducting polymer plug with the corresponding metal bump. Methods of forming and patterning a nickel carbonyl layer are also disclosed.

摘要翻译： 提供了具有暴露的金属端接垫的半导体芯片，以及在其上具有对应的暴露的金属凸块的单独的基板。 在暴露的金属端接垫上形成导电聚合物塞。 在导电聚合物塞上形成一个符合标准的界面层。 半导体芯片的导电聚合物插塞与相应的金属凸块对准。 导电聚合物塞上的一致界面层与相应的金属凸块配合。 一致的界面层被热分解，粘附和永久地附着导电聚合物塞与相应的金属凸块。 还公开了形成和图案化羰基镍层的方法。

公开(公告)号：US06740580B1

公开(公告)日：2004-05-25

申请号：US09389633

申请日：1999-09-03

申请人： Subhash Gupta ,  Chyi S. Chern ,  Mei Sheng Zhou

发明人： Subhash Gupta ,  Chyi S. Chern ,  Mei Sheng Zhou

IPC分类号： H01L214763

CPC分类号： H01L21/76846 ,  H01L21/76873 ,  H01L21/76874 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method to form copper interconnects is described. The method may be used to form single or dual damascene interconnects. The addition of an aluminum barrier layer to the conventional barrier layer creates a superior barrier to copper diffusion. A substrate layer is provided. A dielectric layer is deposited overlying the substrate layer. The dielectric layer patterned to form interconnect trenches. An optional titanium adhesion layer may be deposited. An aluminum barrier layer is deposited overlying the interior surfaces of the trenches. A second barrier layer, comprising for instance titanium and titanium nitride, is deposited overlying the aluminum barrier layer. A copper layer is deposited overlying the second barrier layer and filling the interconnect trenches. The copper layer, the second barrier layer, and the aluminum barrier layer are polished down to the top surface of the dielectric layer to define the copper interconnects, and complete the fabrication of the integrated circuit device.

摘要翻译： 描述形成铜互连的方法。 该方法可以用于形成单镶嵌或双镶嵌互连。 向常规阻挡层添加铝阻挡层产生对铜扩散的优异屏障。 提供基底层。 沉积在基底层上的电介质层。 图案化的电介质层形成互连沟槽。 可以沉积可选的钛粘合层。 覆盖在沟槽的内表面上的铝阻挡层被沉积。 包含例如钛和氮化钛的第二阻挡层沉积在铝阻挡层上。 沉积铜层，覆盖第二阻挡层并填充互连沟槽。 铜层，第二阻挡层和铝阻挡层被抛光到介电层的顶表面以限定铜互连，并且完成集成电路器件的制造。

公开(公告)号：US06656643B2

公开(公告)日：2003-12-02

申请号：US09785116

申请日：2001-02-20

申请人： Subhash Gupta ,  Mei Sheng Zhou

发明人： Subhash Gupta ,  Mei Sheng Zhou

IPC分类号： G03F900

CPC分类号： B82Y10/00 ,  B82Y40/00 ,  G03F1/24 ,  G03F1/54

摘要： An EUV photolithographic mask device and a method of fabricating the same. The EUV photolithographic mask comprises a multi-layer over an EUV masking substrate and a patterned light absorbing layer formed on the multi-layer. The method comprises the steps of forming a multi-layer on an EUV mask substrate, forming a light absorbing layer on the multi-layer, and etching an opening through the light absorbing layer to the multi-layer. The light absorbing layer includes a metal selected from the group comprising nickel, chromium, cobalt, and alloys thereof, and is preferably nickel.

公开(公告)号：US06540841B1

公开(公告)日：2003-04-01

申请号：US09607284

申请日：2000-06-30

申请人： Sudipto Ranendra Roy ,  Subhash Gupta ,  Simon Chooi ,  Xu Yi ,  Yakub Aliyu ,  Mei Sheng Zhou ,  John Leonard Sudijono ,  Paul Kwok Keung Ho

发明人： Sudipto Ranendra Roy ,  Subhash Gupta ,  Simon Chooi ,  Xu Yi ,  Yakub Aliyu ,  Mei Sheng Zhou ,  John Leonard Sudijono ,  Paul Kwok Keung Ho

IPC分类号： B08B700

CPC分类号： B08B1/04 ,  B08B3/04

摘要： A new method and apparatus is provided that can be applied to clean outer edges of semiconductor substrates. Under the first embodiment of the invention, a brush is mounted on the surface of the substrate around the periphery of the substrate, chemicals are fed to the surface that is being cleaned by means of a hollow core on which the cleaning brush is mounted. The surface that is being cleaned rotates at a relatively high speed thereby causing the chemicals that are deposited on this surface (by the brush) to remain in the edge of the surface. Under the second embodiment of the invention, a porous roller is mounted between a chemical reservoir and the surface that is being cleaned, the surface that is being cleaned rotates at a relatively high speed. The chemicals that are deposited by the interfacing porous roller onto the surface that is being cleaned therefore remain at the edge of this surface thereby causing optimum cleaning action of the edge of the surface. After contaminants have been removed in this manner from the surface, the surface can be further cleaned by applying DI water.

摘要翻译： 提供了可用于清洁半导体衬底的外边缘的新方法和装置。 在本发明的第一实施例中，刷子安装在基板周围的基板的表面上，化学品通过其上安装有清洁刷的中空芯被供给到待清洁的表面。 待清洁的表面以相对高的速度旋转，从而使沉积在该表面（由刷子）上的化学物质残留在表面的边缘。 在本发明的第二实施例中，多孔辊安装在化学容器和待清洁的表面之间，待清洁的表面以相对较高的速度旋转。 因此，由界面多孔辊沉积在待清洗的表面上的化学物质保留在该表面的边缘，从而引起表面边缘的最佳清洁作用。 污染物以这种方式从表面除去后，可以通过加入去离子水进一步清洁表面。