公开(公告)号：US10922470B2

公开(公告)日：2021-02-16

申请号：US15933771

申请日：2018-03-23

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： Kuo-Nan Yang ,  Wan-Yu Lo ,  Chung-Hsing Wang ,  Hiranmay Biswas

IPC: G06F30/398 ,  G06F30/392 ,  G06F30/394

Abstract: A method of forming a semiconductor device includes: providing a first circuit having a plurality of circuit cells; analyzing a loading capacitance on a first pin cell connecting a first circuit cell and a second circuit cell in the plurality of circuit cells to determine if the loading capacitance of the first pin cell is larger than a first predetermined capacitance; replacing the first pin cell by a second pin cell for generating a second circuit when the loading capacitance is larger than the first predetermined capacitance, wherein the second pin cell is different from the first pin cell; and generating the semiconductor device according to the second circuit.

公开(公告)号：US10360337B2

公开(公告)日：2019-07-23

申请号：US15903566

申请日：2018-02-23

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： Hiranmay Biswas ,  Kuo-Nan Yang ,  Chung-Hsing Wang

IPC: G06F17/50 ,  G11C11/00 ,  H01L29/76 ,  H01L27/02

Abstract: A method of forming an integrated circuit includes: forming a conductive grid on a semiconductor substrate; selecting a plurality of first conductive lines from a plurality of non-continuous conductive lines according to a first mask layer assigned to the plurality of first conductive lines; selecting a plurality of second conductive lines from the plurality of non-continuous conductive lines according to a second mask layer assigned to the plurality of second conductive lines, wherein the second mask layer different from the first mask layer, and the plurality of second conductive lines is electrically connected to the plurality of first conductive lines via the plurality of continuous conductive lines; and replacing the plurality of second conductive lines by a plurality of third conductive lines respectively, wherein the plurality of third conductive lines is assigned to the first mask layer.

公开(公告)号：US20190164889A1

公开(公告)日：2019-05-30

申请号：US15825363

申请日：2017-11-29

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Hiranmay Biswas ,  Chin-Shen Lin ,  Kuo-Nan Yang ,  Chung-Hsing Wang

IPC: H01L23/528 ,  H01L23/522 ,  G06F17/50 ,  H01L27/02

Abstract: A method of designing an integrated circuit device includes receiving an initial design of an integrated circuit, including a selection and location of a functional group of integrated circuit components, a power grid with multiple layers of conductive lines for supplying power to the components, and vias of one or more initial sizes interconnecting the conductive lines of different layers. The method further includes determining, based on a predetermined criterion such as the existence of unoccupied space for a functional unit, that a via modification can be made. The method further includes substituting the one or more of the via with a modified via of a larger cross-sectional area or a plurality of vias having a larger total cross-sectional area than the initial via. The method further includes confirming that the modified design complies with a predetermined set of design rules.

公开(公告)号：US10074641B2

公开(公告)日：2018-09-11

申请号：US15791320

申请日：2017-10-23

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chien-Ju Chao ,  Chou-Kun Lin ,  Yi-Chuin Tsai ,  Yen-Hung Lin ,  Po-Hsiang Huang ,  Kuo-Nan Yang ,  Chung-Hsing Wang

IPC: H01L27/02 ,  H01L21/8234 ,  H01L27/06 ,  H01L21/768 ,  H01L23/50 ,  H01L23/528 ,  H01L27/092 ,  H01L21/8238 ,  H01L21/822 ,  H01L23/532 ,  H01L21/324

CPC classification number: H01L27/0207 ,  H01L21/324 ,  H01L21/768 ,  H01L21/8221 ,  H01L21/823475 ,  H01L21/823871 ,  H01L23/50 ,  H01L23/528 ,  H01L23/5283 ,  H01L23/5286 ,  H01L23/53238 ,  H01L23/5329 ,  H01L27/0203 ,  H01L27/0688 ,  H01L27/092 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Embodiments of mechanisms for forming power gating cells and virtual power circuits on multiple active device layers are described in the current disclosure. Power gating cells and virtual power circuits are formed on separate active device layers to allow interconnect structure for connecting with the power source be formed on a separate level from the interconnect structure for connecting the power gating cells and the virtual power circuits. Such separation prevents these two types of interconnect structures from competing for the same space. Routings for both types of interconnect structures become easier. As a result, metal lengths of interconnect structures are reduced and the metal widths are increased. Reduced metal lengths and increased metal widths reduce resistance, improves resistance-capacitance (RC) delay and electrical performance, and improves interconnect reliability, such as reducing electro-migration.

公开(公告)号：US09882002B2

公开(公告)日：2018-01-30

申请号：US14987351

申请日：2016-01-04

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Hsiang-Jen Tseng ,  Ting-Wei Chiang ,  Wei-Yu Chen ,  Kuo-Nan Yang ,  Ming-Hsiang Song ,  Ta-Pen Guo

IPC: H01L29/78 ,  H01L21/336 ,  H01L27/088 ,  H01L27/092 ,  H01L21/8234 ,  H01L21/8238 ,  H01L21/84 ,  H01L21/20 ,  H01L29/66 ,  H01L29/08 ,  H01L21/283 ,  H01L21/306 ,  H01L29/417

CPC classification number: H01L29/0847 ,  H01L21/283 ,  H01L21/30604 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823814 ,  H01L21/845 ,  H01L27/0886 ,  H01L27/0924 ,  H01L29/41758 ,  H01L29/66477 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/6681 ,  H01L29/7835 ,  H01L29/785

Abstract: Embodiments of the present disclosure are a semiconductor device, a FinFET device, and a method of forming a FinFET device. An embodiment is a semiconductor device comprising a first semiconductor fin extending above a substrate, a first source region on the first semiconductor fin, and a first drain region on the first semiconductor fin. The first source region has a first width and the first drain region has a second width with the second width being different than the first width.

公开(公告)号：US09397217B2

公开(公告)日：2016-07-19

申请号：US13730052

申请日：2012-12-28

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Hsiang-Jen Tseng ,  Ting-Wei Chang ,  Wei-Yu Chen ,  Kuo-Nan Yang ,  Ming-Hsiang Song ,  Ta-Pen Guo

IPC: H01L29/78 ,  H01L29/66

CPC classification number: H01L29/41775 ,  H01L27/0886 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785

Abstract: The invention relates to a contact structure of a semiconductor device. An exemplary structure for a semiconductor device comprises an insulation region over a substrate; a gate electrode layer over the insulation region comprising a gate middle line; a first contact structure over the insulation region adjacent to the gate electrode layer comprising a first middle line, wherein the first middle line and the gate middle line has a first distance; and a second contact structure over the insulation region on a side of the gate electrode layer opposite to the first contact structure comprising a second middle line, wherein the second middle line and the gate middle line has a second distance greater than the first distance.

Abstract translation: 本发明涉及半导体器件的接触结构。 半导体器件的示例性结构包括在衬底上的绝缘区域; 绝缘区域上的栅极电极层，包括栅极中间线; 在与栅极电极层相邻的绝缘区域上的第一接触结构，包括第一中间线，其中第一中间线和栅极中间线具有第一距离; 以及在与包括第二中间线的第一接触结构相对的栅极电极层的一侧上的绝缘区域上的第二接触结构，其中第二中间线和栅极中间线具有大于第一距离的第二距离。

公开(公告)号：US09058462B2

公开(公告)日：2015-06-16

申请号：US14015846

申请日：2013-08-30

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： King-Ho Tam ,  Yeh-Chi Chang ,  Kuo-Nan Yang ,  Zhe-Wei Jiang ,  Chung-Hsing Wang

IPC: G06F17/50

CPC classification number: G06F17/5081 ,  G06F17/5036 ,  G06F2217/78 ,  G06F2217/82

Abstract: A system and method of producing an integrated circuit using abutted cells having shared polycrystalline silicon on an oxide definition region edge (PODE) includes modeling inter-cell leakage current in a plurality of different cells. Each of the plurality of different cells is abutted with another cell and having the shared PODE. The method also comprises verifying a pre-determined acceptable power consumption of the integrated circuit based on the inter-cell leakage current.

Abstract translation: 使用在氧化物界定区域边缘（PODE）上具有共享多晶硅的邻接单元制造集成电路的系统和方法包括建模多个不同单元中的单元间漏电流。 多个不同的单元中的每一个都与另一个单元相邻并具有共享的PODE。 该方法还包括基于单元间漏电流验证集成电路的预定可接受功耗。

公开(公告)号：US08937358B2

公开(公告)日：2015-01-20

申请号：US13874055

申请日：2013-04-30

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Kuo-Nan Yang ,  Chou-Kun Lin ,  Jerry Chang-Jui Kao ,  Yi-Chuin Tsai ,  Chien-Ju Chao ,  Chung-Hsing Wang

IPC: H01L21/70 ,  H01L27/07

CPC classification number: H01L29/66545 ,  H01L21/823412 ,  H01L27/0207 ,  H01L27/0705 ,  H01L27/11807

Abstract: An integrated circuit includes a first and a second standard cell. The first standard cell includes a first gate electrode, and a first channel region underlying the first gate electrode. The first channel region has a first channel doping concentration. The second standard cell includes a second gate electrode, and a second channel region underlying the second gate electrode. The second channel region has a second channel doping concentration. A dummy gate includes a first half and a second half in the first and the second standard cells, respectively. The first half and the second half are at the edges of the first and the second standard cells, respectively, and are abutted to each other. A dummy channel is overlapped by the dummy gate. The dummy channel has a third channel doping concentration substantially equal to a sum of the first channel doping concentration and the second channel doping concentration.

公开(公告)号：US20140239410A1

公开(公告)日：2014-08-28

申请号：US13829484

申请日：2013-03-14

Applicant: Taiwan Semiconductor Manufacturing Company Ltd.

Inventor： Kuo-Nan Yang ,  Chou-Kun Lin ,  Jerry Chang-Jui Kao ,  Yi-Chuin Tsai ,  Chien-Ju Chao ,  Chung-Hsing Wang

IPC: H01L27/02

CPC classification number: H01L27/0207 ,  H01L27/11807

Abstract: A die includes a plurality of rows of standard cells. Each of all standard cells in the plurality of rows of standard cells includes a transistor and a source edge, wherein a source region of the transistor is adjacent to the source edge. No drain region of any transistor in the each of all standard cells is adjacent to the source region.

Abstract translation: 芯片包括多行标准单元。 多行标准单元中的每个标准单元包括晶体管和源极边缘，其中晶体管的源极区域与源极边缘相邻。 所有标准单元中的每一个中的任何晶体管的漏极区域都不与源极区域相邻。

公开(公告)号：US20250117563A1

公开(公告)日：2025-04-10

申请号：US18982045

申请日：2024-12-16

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Jack Liu ,  Kuo-Nan Yang

IPC: G06F30/392 ,  G06F30/3953 ,  G06F119/06 ,  H01L23/522 ,  H10D62/10

Abstract: One aspect of this description relates to an integrated circuit (IC) structure including a first layer and a second layer. The first layer includes a first metal structure coupled to a first power supply having a first voltage level and a second metal structure coupled to a second power supply having a second voltage level different from the first voltage level. The second layer is formed over the first layer. The second layer includes a first nano-sheet device coupled to the first metal structure and a second nano-sheet device adjacent to the first nano-sheet device. The second nano-sheet device is coupled to the second metal structure. A distance between the first nano-sheet device and the second nano-sheet device is less than a minimum n-well to n-well spacing.