公开(公告)号：US20230253338A1

公开(公告)日：2023-08-10

申请号：US18302461

申请日：2023-04-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Po-Han Wang ,  Hung-Jui Kuo ,  Yu-Hsiang Hu

IPC: H01L23/538 ,  H01L25/16 ,  H01L21/56 ,  H01L21/768 ,  H01L21/288 ,  H01L23/00 ,  H01L25/10 ,  H01L21/48 ,  H01L23/31 ,  H01L21/683 ,  H01L25/00

CPC classification number: H01L23/5389 ,  H01L23/5384 ,  H01L23/5386 ,  H01L25/16 ,  H01L21/56 ,  H01L21/76802 ,  H01L21/76873 ,  H01L21/76879 ,  H01L21/2885 ,  H01L21/76834 ,  H01L24/24 ,  H01L24/19 ,  H01L25/105 ,  H01L21/4857 ,  H01L21/486 ,  H01L23/3128 ,  H01L21/568 ,  H01L21/6835 ,  H01L25/50 ,  H01L25/0657

Abstract: In an embodiment, a device includes: a molding compound; an integrated circuit die encapsulated in the molding compound; a through via adjacent the integrated circuit die; and a redistribution structure over the integrated circuit die, the molding compound, and the through via, the redistribution structure electrically connected to the integrated circuit die and the through via, the redistribution structure including: a first dielectric layer disposed over the molding compound; a first conductive via extending through the first dielectric layer; a second dielectric layer disposed over the first dielectric layer and the first conductive via; and a second conductive via extending through the second dielectric layer and into a portion of the first conductive via, an interface between the first conductive via and the second conductive via being non-planar.

公开(公告)号：US20230215831A1

公开(公告)日：2023-07-06

申请号：US18182470

申请日：2023-03-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hung-Chun Cho ,  Hung-Jui Kuo ,  Yu-Hsiang Hu ,  Sih-Hao Liao

IPC: H01L23/00 ,  H01L25/065 ,  H01L25/00 ,  H01L25/18 ,  H01L23/29

CPC classification number: H01L24/20 ,  H01L25/0652 ,  H01L25/50 ,  H01L24/19 ,  H01L24/82 ,  H01L24/96 ,  H01L25/18 ,  H01L23/296 ,  H01L23/295 ,  H01L21/561

Abstract: In an embodiment, a method includes forming a conductive feature adjacent to a substrate; treating the conductive feature with a protective material, the protective material comprising an inorganic core with an organic coating around the inorganic core, the treating the conductive feature comprising forming a protective layer over the conductive feature; and forming an encapsulant around the conductive feature and the protective layer. In another embodiment, the method further includes, before forming the encapsulant, rinsing the protective layer with water. In another embodiment, the protective layer is selectively formed over the conductive feature.

公开(公告)号：US11646220B2

公开(公告)日：2023-05-09

申请号：US17650926

申请日：2022-02-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chen-Hua Yu ,  An-Jhih Su ,  Chi-Hsi Wu ,  Der-Chyang Yeh ,  Ming Shih Yeh ,  Jing-Cheng Lin ,  Hung-Jui Kuo

IPC: H01L21/768 ,  H01L21/48 ,  H01L23/48 ,  H01L23/498 ,  H01L23/522 ,  H01L23/538 ,  H01L23/00

CPC classification number: H01L21/76805 ,  H01L21/486 ,  H01L21/4853 ,  H01L21/76813 ,  H01L23/481 ,  H01L23/49827 ,  H01L23/5222 ,  H01L23/5226 ,  H01L23/5384 ,  H01L24/24 ,  H01L24/27 ,  H01L24/28 ,  H01L24/73 ,  H01L24/82 ,  H01L24/13 ,  H01L24/32 ,  H01L24/48 ,  H01L2224/04042 ,  H01L2224/05548 ,  H01L2224/05567 ,  H01L2224/244 ,  H01L2224/24147 ,  H01L2224/29144 ,  H01L2224/29147 ,  H01L2224/32145 ,  H01L2224/32265 ,  H01L2224/73215 ,  H01L2224/73217 ,  H01L2224/73227 ,  H01L2224/73267 ,  H01L2224/821 ,  H01L2224/82051 ,  H01L2224/82951 ,  H01L2224/83191 ,  H01L2224/83815 ,  H01L2224/83895

Abstract: A method includes forming a metal layer extending into openings of a dielectric layer to contact a first metal pad and a second metal pad, and bonding a bottom terminal of a component device to the metal layer. The metal layer has a first portion directly underlying and bonded to the component device. A raised via is formed on the metal layer, and the metal layer has a second portion directly underlying the raised via. The metal layer is etched to separate the first portion and the second portion of the metal layer from each other. The method further includes coating the raised via and the component device in a dielectric layer, revealing the raised via and a top terminal of the component device, and forming a redistribution line connecting the raised via to the top terminal.

公开(公告)号：US20230064162A1

公开(公告)日：2023-03-02

申请号：US17461656

申请日：2021-08-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsing-Chieh Lee ,  Hung-Jui Kuo ,  Ming-Tan Lee ,  Ting Yi Lin

IPC: G03F7/004 ,  H01L23/00

Abstract: A semiconductor device and method of manufacturing a semiconductor device is disclosed herein including creating a photoresist mixture that includes a surfactant, and a base solvent; one or more boiling point modifying solvents having a boiling point higher in temperature than the base solvent; and one or more hydrophilicity modifying solvents that are more hydrophilic than the base solvent; depositing the photoresist mixture onto a substrate comprising a plurality of UBMLs using a wet film process; performing a pre-bake process to cure the photoresist; and patterning the photoresist.

公开(公告)号：US20230011701A1

公开(公告)日：2023-01-12

申请号：US17371204

申请日：2021-07-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hung-Jui Kuo ,  Ting-Yang Yu ,  Ming-Tan Lee

IPC: G03F7/20 ,  G03F1/46

Abstract: In an embodiment, an apparatus includes an energy source, a support platform for holding a wafer, an optical path extending from the energy source to the support platform, and a photomask aligned such that a patterned major surface of the photomask is parallel to the force of gravity, where the optical path passes through the photomask, where the patterned major surface of the photomask is perpendicular to a topmost surface of the support platform.

公开(公告)号：US20220352086A1

公开(公告)日：2022-11-03

申请号：US17868345

申请日：2022-07-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chen-Hua Yu ,  Hung-Jui Kuo ,  Hui-Jung Tsai

IPC: H01L23/538 ,  H01L23/485 ,  H01L23/00 ,  H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H01L21/48 ,  H01L21/56 ,  H01L23/31 ,  H01L23/498

Abstract: A method embodiment includes forming a patterned first photo resist over a seed layer. A first opening in the patterned first photo resist exposes the seed layer. The method further includes plating a first conductive material in the first opening on the seed layer, removing the patterned first photo resist, and after removing the patterned first photo resist, forming a patterned second photo resist over the first conductive material. A second opening in the patterned second photo resist exposes a portion of the first conductive material. The method further includes plating a second conductive material in the second opening on the first conductive material, removing the patterned second photo resist, and after removing the patterned second photo resist, depositing a dielectric layer around the first conductive material and the second conductive material.

公开(公告)号：US20220208688A1

公开(公告)日：2022-06-30

申请号：US17654620

申请日：2022-03-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jhih-Yu Wang ,  Yung-Chi Chu ,  Sih-Hao Liao ,  Yu-Hsiang Hu ,  Hung-Jui Kuo

IPC: H01L23/544 ,  H01L25/10 ,  H01L23/00 ,  H01L23/31 ,  H01L23/538 ,  H01L21/48 ,  H01L21/56 ,  H01L21/78 ,  H01L25/00

Abstract: A method includes encapsulating a device die in an encapsulating material, forming a first dielectric layer over the device die and the encapsulating material, forming first redistribution lines extending into the first dielectric layer to electrically couple to the device die, forming an alignment mark over the first dielectric layer, wherein the alignment mark includes a plurality of elongated strips, forming a second dielectric layer over the first redistribution lines and the alignment mark, and forming second redistribution lines extending into the second dielectric layer to electrically couple to the first redistribution lines. The second redistribution lines are formed using the alignment mark for alignment.

公开(公告)号：US11322450B2

公开(公告)日：2022-05-03

申请号：US16164752

申请日：2018-10-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Hsiang Hu ,  Chen-Hua Yu ,  Hung-Jui Kuo

IPC: H01L23/538 ,  H01L23/31 ,  H01L23/00 ,  H01L21/56 ,  H01L21/768 ,  H01L21/027 ,  H01L23/48 ,  H01L25/18 ,  H01L25/00 ,  H01L21/48 ,  H01L21/683

Abstract: A chip package including a semiconductor die, an insulating encapsulant, and a first redistribution layer is provided. The insulating encapsulant encapsulates the semiconductor die. The first redistribution layer is provided over the semiconductor die and the encapsulant and includes a first redistribution portion and a second redistribution portion in contact with the first redistribution portion. The first redistribution portion is between the second redistribution portion and the semiconductor die. The first redistribution portion includes a first dielectric portion and a plurality of first conductive features embedded in the first dielectric portion. The plurality of first conductive features electrically connects the semiconductor die to the second redistribution portion. The second redistribution portion includes a second dielectric portion and a plurality of second conductive features embedded in the second dielectric portion and connected to the first conductive features. A top surface of the second dielectric portion is substantially level with top surfaces of the plurality of second conductive features. A method of forming the chip package is also provided.

公开(公告)号：US11282804B2

公开(公告)日：2022-03-22

申请号：US16714811

申请日：2019-12-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wei-Chih Chen ,  Hung-Jui Kuo ,  Yu-Hsiang Hu ,  Sih-Hao Liao

IPC: H01L23/00 ,  H01L23/29

Abstract: A package structure and a method of forming the same are provided. The package structure includes a die, an encapsulant, a polymer layer and a redistribution layer. The encapsulant laterally encapsulates the die. The polymer layer is on the encapsulant and the die. The polymer layer includes an extending portion having a bottom surface lower than a top surface of the die. The redistribution layer penetrates through the polymer layer to connect to the die.

公开(公告)号：US11164839B2

公开(公告)日：2021-11-02

申请号：US16413591

申请日：2019-05-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wei-Chih Chen ,  Hung-Jui Kuo ,  Yu-Hsiang Hu ,  Sih-Hao Liao ,  Po-Han Wang ,  Yung-Chi Chu ,  Hung-Chun Cho

IPC: H01L23/00 ,  H01L23/31 ,  H01L23/498 ,  H01L23/538 ,  H01L21/48 ,  H01L21/56 ,  H01L25/00 ,  H01L25/065 ,  H01L21/683 ,  C09J165/00

Abstract: A package structure includes a semiconductor die and a redistribution circuit structure. The redistribution circuit structure is disposed on and electrically connected to the semiconductor die and includes a patterned conductive layer, a dielectric layer, and an inter-layer film. The dielectric layer is disposed on the patterned conductive layer. The inter-layer film is sandwiched between the dielectric layer and the patterned conductive layer, and the patterned conductive layer is separated from the dielectric layer through the inter-layer film.