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108 条记录 (耗时 0.037 秒)

    Efficient multi-station MRI
    62.
    发明授权
    Efficient multi-station MRI 有权
    高效多站MRI

    公开(公告)号：US09157979B2

    公开(公告)日：2015-10-13

    申请号：US13098805

    申请日：2011-05-02

    申请人： Mitsue Miyazaki ,  Katsumi Nakamura ,  Akiyoshi Yamamoto

    发明人： Mitsue Miyazaki ,  Katsumi Nakamura ,  Akiyoshi Yamamoto

    IPC分类号： A61B5/05 ,  G01R33/567 ,  G01R33/54 ,  G01R33/563

    CPC分类号： A61B5/0555 ,  A61B5/055 ,  G01R33/543 ,  G01R33/5635 ,  G01R33/56383 ,  G01R33/5673

    摘要： A magnetic resonance imaging (MRI) system includes at least one controller configured to first acquire at least MRI locator image data for different portions of patient anatomy at each of different imaging stations for a defined multi-station locator sequence. An operator may interface with a respectively corresponding displayed locator image for each imaging station to set diagnostic scan sequence parameters for subsequent diagnostic MRI scans of corresponding portions of patient anatomy. Diagnostic MRI scan data is automatically acquired at each of the imaging stations in a multi-station diagnostic scan sequence that, if desired, can be seamlessly continued without operator interruption once begun.

    摘要翻译： 磁共振成像（MRI）系统包括至少一个控制器，其被配置为针对定义的多站定位器序列，首先在每个不同成像站处首先获取用于患者解剖结构的不同部分的至少MRI定位器图像数据。 操作者可以与每个成像站的分别对应的显示的定位器图像接口，以设置诊断扫描序列参数，以用于患者解剖结构对应部分的后续诊断MRI扫描。 诊断MRI扫描数据在多站诊断扫描序列中的每个成像站处被自动获取，如果需要，可以无缝地继续，而无需操作员中断一旦开始。

    METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE
    63.
    发明申请
    METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE 有权
    制造半导体器件的方法

    公开(公告)号：US20150255290A1

    公开(公告)日：2015-09-10

    申请号：US14433191

    申请日：2012-12-07

    申请人： Fumihito Masuoka ,  Katsumi Nakamura ,  Takao Kachi

    发明人： Fumihito Masuoka ,  Katsumi Nakamura ,  Takao Kachi

    IPC分类号： H01L21/265 ,  H01L29/10 ,  H01L29/06

    CPC分类号： H01L21/26513 ,  H01L21/2252 ,  H01L21/26586 ,  H01L29/0615 ,  H01L29/0619 ,  H01L29/0638 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/2003 ,  H01L29/6606 ,  H01L29/6609 ,  H01L29/66204 ,  H01L29/861

    摘要： An insulating film (2) is formed on a main surface of a semiconductor substrate (1) that includes an active region and a termination region. The insulating film (2) in the active region is etched to form an opening (3). The insulating film (2) is used as a mask and an impurity is implanted into the semiconductor substrate (1) in a direction tilted by 20° or more from a direction normal to the main surface of the semiconductor substrate (1) while rotating the semiconductor substrate (1) to form a diffusion layer (7) in the active region. The diffusion layer (7) extends wider than the opening (3) up to below the insulating film (2) on the termination region side.

    摘要翻译： 绝缘膜（2）形成在包括有源区和端接区的半导体衬底（1）的主表面上。 有源区域中的绝缘膜（2）被蚀刻以形成开口（3）。 绝缘膜（2）用作掩模，并且在从半导体衬底（1）的主表面垂直的方向上倾斜20°或更大的方向将杂质注入到半导体衬底（1）中，同时旋转 半导体衬底（1）以在有源区中形成扩散层（7）。 扩散层（7）在开口（3）上延伸到终端区域侧的绝缘膜（2）的下方。

    SEMICONDUCTOR DEVICE
    64.
    发明申请
    SEMICONDUCTOR DEVICE 有权
    半导体器件

    公开(公告)号：US20150014741A1

    公开(公告)日：2015-01-15

    申请号：US14370048

    申请日：2012-03-05

    申请人： Ze Chen ,  Katsumi Nakamura

    发明人： Ze Chen ,  Katsumi Nakamura

    IPC分类号： H01L29/739 ,  H01L29/06 ,  H01L29/423

    CPC分类号： H01L29/0634 ,  H01L29/0619 ,  H01L29/1095 ,  H01L29/404 ,  H01L29/4236 ,  H01L29/7397

    摘要： A semiconductor device includes a semiconductor substrate in which an active region and an edge termination region are defined, a semiconductor element formed in the active region, and first to fourth P layers formed in a region spanning from an edge portion of the active region to the edge termination region in the surface of the semiconductor substrate. The first to fourth P layers respectively have surface concentrations P(1) to P(4) that decrease in this order, bottom-end distances D(1) to D(4) that increase in this order, and distances B(1) to B(4) to the edge of the semiconductor substrate that increase in this order. The surface concentration P(4) is 10 to 1000 times the impurity concentration of the semiconductor substrate, and the bottom-end distance D(4) is in the range of 15 to 30 μm.

    摘要翻译： 半导体器件包括其中限定有源区和边缘终端区的半导体衬底，形成在有源区中的半导体元件，以及形成在从有源区的边缘部分到 边缘端接区域。 第一至第四P层分别具有按此顺序降低的表面浓度P（1）至P（4），以该顺序增加的底端距离D（1）至D（4），距离B（1） 到B（4）到依次增加的半导体衬底的边缘。 表面浓度P（4）是半导体衬底的杂质浓度的10〜1000倍，底端距离D（4）在15〜30μm的范围内。

    Semiconductor device
    65.
    发明授权
    Semiconductor device 有权
    半导体器件

    公开(公告)号：US08686469B2

    公开(公告)日：2014-04-01

    申请号：US13093397

    申请日：2011-04-25

    申请人： Katsumi Nakamura

    发明人： Katsumi Nakamura

    IPC分类号： H01L29/02

    CPC分类号： H01L29/861 ,  H01L23/3171 ,  H01L29/0619 ,  H01L29/402 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A semiconductor device includes a semiconductor substrate having a diode active region and an edge termination region adjacent to each other, a first region of a first conductivity type in the diode active region, a second region of a second conductivity type, a third region of the first conductivity type in the edge termination region, and a fourth region of the second conductivity type. The first region and the third region share a drift region of the first conductivity type. The first region and the third region share a fifth region of the first conductivity type. The drift region in the third region is greater in number of crystal defects per unit volume than the drift region in the first region in order that the drift region in the third region is shorter in carrier lifetime than the drift region in the first region.

    摘要翻译： 半导体器件包括具有二极管有源区和相邻的边缘终端区的半导体衬底，二极管有源区中的第一导电类型的第一区，第二导电类型的第二区， 边缘终止区域中的第一导电类型和第二导电类型的第四区域。 第一区域和第三区域共享第一导电类型的漂移区域。 第一区域和第三区域共享第一导电类型的第五区域。 与第一区域的漂移区域相比，第三区域中的漂移区域比单位体积的晶体缺陷数多于第一区域中的漂移区域，使得第三区域中的漂移区域的载流子寿命更短。

    Flow control valve and method for manufacturing the same
    66.
    发明授权
    Flow control valve and method for manufacturing the same 有权
    流量控制阀及其制造方法

    公开(公告)号：US08434506B2

    公开(公告)日：2013-05-07

    申请号：US12997655

    申请日：2009-06-23

    申请人： Katsumi Nakamura ,  Shingo Iguchi ,  Yoshiki Ihara

    发明人： Katsumi Nakamura ,  Shingo Iguchi ,  Yoshiki Ihara

    IPC分类号： F16K1/22

    CPC分类号： F16K1/2263 ,  F02D9/1045 ,  F02D9/107 ,  F02M35/10085 ,  F02M35/10255 ,  F16K27/0218 ,  Y10T29/49426 ,  Y10T137/0525 ,  Y10T137/6048

    摘要： A flow control valve in which corrosion is less likely to occur in the vicinity of a radial step portion in a gas passage of a housing and a method for manufacturing the same are provided. A flow control valve includes: a housing formed with a gas passage including a first cylinder member accommodating portion, a second cylinder member accommodating portion, and a radial step portion; a first cylinder member accommodated in the first cylinder member accommodating portion; a second cylinder member accommodated in the second cylinder member accommodating portion; and a valve body that is rotatably arranged inside the first cylinder member and the second cylinder member in the radial direction. The housing is formed of cast iron. At least surfaces of the first cylinder member and the second cylinder member are formed of a highly corrosion resistant material. At least one of a first axial end surface and a second axial end surface includes an opposing portion that opposes the radial step portion in the axial direction. A gas seal structure is arranged between the opposing portion and the radial step portion.

    摘要翻译： 提供了一种流量控制阀及其制造方法，其中在壳体的气体通道中的径向台阶部分附近不太可能发生腐蚀。 流量控制阀包括：形成有气体通道的壳体，包括第一气缸构件容纳部分，第二气缸构件容纳部分和径向台阶部分; 容纳在所述第一气缸部件容纳部中的第一气缸部件; 容纳在所述第二气缸构件容纳部分中的第二气缸构件; 以及阀体，其在径向上可旋转地布置在第一气缸构件和第二气缸构件的内部。 外壳由铸铁制成。 第一气缸构件和第二气缸构件的至少表面由耐腐蚀性高的材料形成。 第一轴向端面和第二轴向端面中的至少一个包括在轴向上与径向台阶部分相对的相对部分。 气体密封结构布置在相对部分和径向台阶部分之间。

    SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME
    67.
    发明申请
    SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME 审中-公开
    半导体器件及其制造方法

    公开(公告)号：US20120228700A1

    公开(公告)日：2012-09-13

    申请号：US13237309

    申请日：2011-09-20

    申请人： Akito Nishii ,  Katsumi Nakamura

    发明人： Akito Nishii ,  Katsumi Nakamura

    IPC分类号： H01L29/78 ,  H01L21/20

    CPC分类号： H01L29/861 ,  H01L29/0615 ,  H01L29/0696 ,  H01L29/083 ,  H01L29/423 ,  H01L29/66348 ,  H01L29/7397

    摘要： A semiconductor device includes: an N-type drift layer; a P-type anode layer on the N-type drift layer; a trench penetrating the P-type anode layer; a conductive substance embedded in the trench via an insulating film; and an N-type buffer layer between the N-type drift layer and the P-type anode layer and having impurity concentration which is higher than that of the N-type drift layer.

    摘要翻译： 一种半导体器件包括：N型漂移层; N型漂移层上的P型阳极层; 穿透P型阳极层的沟槽; 通过绝缘膜嵌入沟槽中的导电物质; 以及在N型漂移层和P型阳极层之间的N型缓冲层，其杂质浓度高于N型漂移层的杂质浓度。

    Semiconductor device and manufacturing method thereof
    69.
    发明授权
    Semiconductor device and manufacturing method thereof 失效
    半导体装置及其制造方法

    公开(公告)号：US07253031B2

    公开(公告)日：2007-08-07

    申请号：US10978440

    申请日：2004-11-02

    申请人： Tetsuo Takahashi ,  Katsumi Nakamura ,  Tadaharu Minato ,  Masana Harada

    发明人： Tetsuo Takahashi ,  Katsumi Nakamura ,  Tadaharu Minato ,  Masana Harada

    IPC分类号： H01L21/332 ,  H01L21/336

    CPC分类号： H01L29/7397 ,  H01L29/0692 ,  H01L29/0696 ,  H01L29/66348 ,  H01L29/66356 ,  H01L29/7391 ,  H01L29/7455 ,  H01L29/749 ,  H01L29/861 ,  H01L29/868

    摘要： A pin diode is formed by a p+ collector region, an n type buffer region, an n− region and an n+ cathode region. A trench is formed from the surface of n+ cathode region through n+ cathode region to reach n− region. An insulating film is formed along an inner wall surface of trench. A gate electrode layer is formed to oppose to the sidewall of n+ cathode region with insulating film interposed. A cathode electrode is formed to be electrically connected to n+ cathode region. An anode electrode is formed to be electrically connected to p+ collector region. The n+ cathode region is formed entirely over the surface between trenches extending parallel to each other. Thus, a power semiconductor device in which gate control circuit is simplified and which has good on property can be obtained.

    摘要翻译： pin二极管由p + +集电极区，n型缓冲区，n + SUP区和n + + SUP阴极区形成。 从n + +阴极区域的表面形成沟槽，以通过n + + + / - >阴极区域形成沟槽，以达到n + - SUP区域。 绝缘膜沿沟槽的内壁表面形成。 形成与绝缘膜插入的n + +阴极区的侧壁相对的栅极电极层。 阴极电极形成为与n + +阴极区电连接。 阳极电极形成为与p + +集电极区域电连接。 阴极区域整体形成在彼此平行延伸的沟槽之间的表面上。 因此，可以获得其中简化了栅极控制电路并且具有良好的性能的功率半导体器件。

    Insulated gate transistor
    70.
    发明授权
    Insulated gate transistor 有权
    绝缘栅晶体管

    公开(公告)号：US07250345B2

    公开(公告)日：2007-07-31

    申请号：US10976855

    申请日：2004-11-01

    申请人： Katsumi Nakamura ,  Shigeru Kusunoki ,  Hideki Nakamura

    发明人： Katsumi Nakamura ,  Shigeru Kusunoki ,  Hideki Nakamura

    IPC分类号： H01L21/336

    CPC分类号： H01L29/7802 ,  H01L29/0619 ,  H01L29/0696 ,  H01L29/0847 ,  H01L29/402 ,  H01L29/407 ,  H01L29/4232 ,  H01L29/4238 ,  H01L29/456 ,  H01L29/495 ,  H01L29/4958 ,  H01L29/66348 ,  H01L29/66734 ,  H01L29/7395 ,  H01L29/7397 ,  H01L29/7813

    摘要： A semiconductor device of the present invention is provided with a power device which has a semiconductor substrate having a first main surface and a second main surface that are opposed to each other and an insulating gate structure on the first main surface side, wherein a main current flows between the first main surface and the second main surface, that is to say, is provided with an insulating gate type MOS transistor structure wherein the thickness (t1) of the semiconductor substrate is no less than 50 μm and no greater than 250 μm and a low ON voltage and a high withstanding capacity against breakdown are implemented in the first main surface. Thereby, a low ON voltage, the maintaining of the withstanding capacity against breakdown and the reduction of a switching loss on the high voltage side can be implemented.

    摘要翻译： 本发明的半导体器件具有电源装置，该功率器件具有：具有彼此相对的第一主表面和第二主表面的半导体衬底，以及在第一主表面侧的绝缘栅极结构，其中主电流 在第一主表面和第二主表面之间流动，即具有绝缘栅型MOS晶体管结构，其中半导体衬底的厚度（t 1> 1）不小于50 在第一主表面上实施了不超过250个妈妈的低导通电压和高耐破坏能力。 因此，可以实现低导通电压，耐击穿能力的保持和高压侧的开关损耗的降低。