公开(公告)号：US07382026B2

公开(公告)日：2008-06-03

申请号：US11889677

申请日：2007-08-15

申请人： Yuuichi Hirano ,  Takashi Ipposhi ,  Shigeto Maegawa ,  Koji Nii

发明人： Yuuichi Hirano ,  Takashi Ipposhi ,  Shigeto Maegawa ,  Koji Nii

IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L31/00

CPC分类号： H01L21/84 ,  H01L27/0207 ,  H01L27/11 ,  H01L27/1108 ,  H01L27/1203 ,  Y10S257/903 ,  Y10S257/904

摘要： A contact connected to a word line is formed on a gate electrode of an access transistor of an SRAM cell. The contact passes through an element isolation insulating film to reach an SOI layer. A body region of a driver transistor and that of the access transistor are electrically connected with each other through the SOI layer located under the element isolation insulating film. Therefore, the access transistor is in a DTMOS structure having the gate electrode connected with the body region through the contact, which in turn is also electrically connected to the body region of the driver transistor. Thus, operations can be stabilized while suppressing increase of an area for forming the SRAM cell.

公开(公告)号：US07339238B2

公开(公告)日：2008-03-04

申请号：US11510582

申请日：2006-08-28

申请人： Shigenobu Maeda ,  Takashi Ipposhi ,  Yuuichi Hirano

发明人： Shigenobu Maeda ,  Takashi Ipposhi ,  Yuuichi Hirano

IPC分类号： H01L29/76

CPC分类号： H01L21/84 ,  H01L27/0629 ,  H01L27/0808 ,  H01L27/0811 ,  H01L27/1203 ,  H01L29/66181 ,  H01L29/66545 ,  H01L29/94

摘要： It is an object to obtain a semiconductor device including a capacitance having a great Q-value. In an SOI substrate comprising a support substrate (165), a buried oxide film (166) and an SOI layer (171), an isolating oxide film 167 (167a to 167c) is selectively formed in an upper layer portion of the SOI layer (171) with a part of the SOI layer (171) remaining as a P− well region (169). Consequently, an isolation (partial isolation) structure is obtained. An N+ diffusion region (168) is formed in the SOI layer (171) between the isolating oxide films (167a) and (167b) and a P+ diffusion region (170) is formed in the SOI layer (171) between the isolating oxide films (167b) and (167c). Consequently, there is obtained a junction type variable capacitance (C23) having a PN junction surface of the P− well region (169) provided under the isolating oxide film (167b) and the N+ diffusion region (168).

摘要翻译： 本发明的目的是获得包括具有大Q值的电容的半导体器件。 在包括支撑衬底（165），掩埋氧化膜（166）和SOI层（171）的SOI衬底中，在SOI的上层部分中选择性地形成隔离氧化膜167（167a至167c） 层（171）与SOI层（171）的一部分保持为阱区（169）。 因此，获得隔离（部分隔离）结构。 在隔离氧化膜（167a）和（167b）之间的SOI层（171）中形成有N + +扩散区（168）和P + 区域（170）形成在隔离氧化膜（167b）和（167c）之间的SOI层（171）中。 因此，获得了具有设置在隔离氧化膜（167b）下面的P阱区域（169）的PN结表面的结型可变电容（C23）和N

公开(公告)号：US20080042237A1

公开(公告)日：2008-02-21

申请号：US11873907

申请日：2007-10-17

申请人： Toshiaki IWAMATSU ,  Takashi Ipposhi

发明人： Toshiaki IWAMATSU ,  Takashi Ipposhi

IPC分类号： H01L29/80

CPC分类号： H01L27/0617 ,  H01L21/76283 ,  H01L21/84 ,  H01L27/0629 ,  H01L27/1203 ,  H01L27/13 ,  H01L28/10 ,  H01L28/20 ,  H01L29/665 ,  H01L29/6659 ,  H01L29/7833

摘要： Plural trench isolation films are provided with portions of an SOI layer interposed therebetween in a surface of the SOI layer in a resistor region (RR) where a spiral inductor (SI) is to be provided. Resistive elements are formed on the trench isolation films, respectively. Each of the trench isolation films includes a central portion which passes through the SOI layer and reaches a buried oxide film to include a full-trench isolation structure, and opposite side portions each of which passes through only a potion of the OSI layer and is located on the SOI layer 3 to include a partial-trench isolation structure. Thus, each of the trench isolation films includes a hybrid-trench isolation structure.

摘要翻译： 多个沟槽隔离膜在其中设置有螺旋电感器（SI）的电阻器区域（RR）中的SOI层的表面中设置有SOI层的部分。 电阻元件分别形成在沟槽隔离膜上。 每个沟槽隔离膜包括穿过SOI层并到达掩埋氧化膜以包括全沟槽隔离结构的中心部分，以及相对的侧部，其每个仅穿过OSI层的一部分并且位于 在SOI层3上，以包括部分沟槽隔离结构。 因此，每个沟槽隔离膜包括混合沟槽隔离结构。

公开(公告)号：US07332793B2

公开(公告)日：2008-02-19

申请号：US11705748

申请日：2007-02-14

申请人： Takashi Ipposhi

发明人： Takashi Ipposhi

IPC分类号： H01L29/00

CPC分类号： H01L27/1203 ,  H01L21/84 ,  H01L23/5227 ,  H01L2924/0002 ,  H01L2924/00

摘要： A transistor region is a region where a plurality of MOS transistors, including an MOS transistor, are formed, and a dummy region is a region lying under a spiral inductor. In the dummy region, a plurality of dummy active layers are disposed in the main surface of an SOI substrate and a plurality of dummy gate electrodes are disposed covering the respective dummy active layers. The arrangement pattern of the dummy active layers and the arrangement pattern of the dummy gate electrodes nearly match, so that the dummy gate electrodes are aligned accurately on the dummy active layers.

摘要翻译： 晶体管区域是形成包括MOS晶体管的多个MOS晶体管的区域，虚设区域是位于螺旋电感器下面的区域。 在虚拟区域中，在SOI衬底的主表面上设置多个虚设有源层，并且设置覆盖各个虚拟有源层的多个虚拟栅极电极。 虚拟有源层的布置图案和虚拟栅极电极的布置图案几乎一致，使得虚拟栅电极在虚拟有源层上精确对准。

公开(公告)号：US07303950B2

公开(公告)日：2007-12-04

申请号：US11034938

申请日：2005-01-14

申请人： Yasuo Yamaguchi ,  Shigeto Maegawa ,  Takashi Ipposhi ,  Toshiaki Iwamatsu ,  Shigenobu Maeda ,  Yuuichi Hirano ,  Takuji Matsumoto ,  Shoichi Miyamoto

发明人： Yasuo Yamaguchi ,  Shigeto Maegawa ,  Takashi Ipposhi ,  Toshiaki Iwamatsu ,  Shigenobu Maeda ,  Yuuichi Hirano ,  Takuji Matsumoto ,  Shoichi Miyamoto

IPC分类号： H01L21/8238

CPC分类号： H01L21/84 ,  H01L27/1203

摘要： A partial oxide film (31) with well regions formed therebeneath isolates transistor formation regions in an SOI layer (3) from each other. A p-type well region (11) is formed beneath part of the partial oxide film (31) which isolates NMOS transistors from each other, and an n-type well region (12) is formed beneath part of the partial oxide film (31) which isolates PMOS transistors from each other. The p-type well region (11) and the n-type well region (12) are formed in side-by-side relation beneath part of the partial oxide film (31) which provides isolation between the NMOS and PMOS transistors. A body region is in contact with the well region (11) adjacent thereto. An interconnect layer formed on an interlayer insulation film (4) is electrically connected to the body region through a body contact provided in the interlayer insulation film (4). A semiconductor device having an SOI structure reduces a floating-substrate effect.

摘要翻译： 在其之间形成的具有阱区的部分氧化物膜（31）将SOI层（3）中的晶体管形成区域彼此隔离。 在部分氧化膜（31）的下部形成p型阱区（11），其将NMOS晶体管彼此隔离，并且在部分氧化膜（31）的一部分下面形成n型阱区（12） ），其将PMOS晶体管彼此隔离。 p型阱区（11）和n型阱区（12）在部分氧化膜（31）的一部分下方并排地形成，其提供NMOS和PMOS晶体管之间的隔离。 身体区域与与其相邻的井区域（11）接触。 形成在层间绝缘膜（4）上的互连层通过设置在层间绝缘膜（4）中的主体接触部电连接到体区。 具有SOI结构的半导体器件减少浮置衬底效应。

公开(公告)号：US07183167B2

公开(公告)日：2007-02-27

申请号：US11011655

申请日：2004-12-15

申请人： Toshiaki Iwamatsu ,  Takashi Ipposhi ,  Takuji Matsumoto ,  Shigenobu Maeda

发明人： Toshiaki Iwamatsu ,  Takashi Ipposhi ,  Takuji Matsumoto ,  Shigenobu Maeda

IPC分类号： H01L21/336

CPC分类号： H01L21/2652 ,  H01L21/76264 ,  H01L21/76283 ,  H01L21/84 ,  H01L27/1203

摘要： The present invention provides a method of fabricating a semiconductor device in which deterioration in a transistor characteristic is prevented by preventing a channel stop implantation layer from being formed in an active region. A resist mask is formed so as to have an opening over a region in which a PMOS transistor is formed. Channel stop implantation is performed with energy by which ions pass through a partial isolation oxide film and a peak of an impurity profile is generated in an SOI layer, thereby forming a channel stop layer in the SOI layer under the partial isolation oxide film, that is, an isolation region. An impurity to be implanted here is an N-type impurity. In the case of using phosphorus, its implantation energy is set to, for example, 60 to 120 keV, and the density of the channel stop layer is set to 1×1017 to 1×1019/cm3. At this time, the impurity of channel stop implantation is not stopped in the SOI layer corresponding to the active region.

公开(公告)号：US20060267012A1

公开(公告)日：2006-11-30

申请号：US11498800

申请日：2006-08-04

申请人： Shigeto Maegawa ,  Takashi Ipposhi ,  Toshiaki Iwamatsu ,  Shigenobu Maeda ,  Il-Jung Kim ,  Kazuhito Tsutsumi ,  Hirotada Kuriyama ,  Yoshiyuki Ishigaki ,  Motomu Ukita ,  Toshiaki Tsutsumi

发明人： Shigeto Maegawa ,  Takashi Ipposhi ,  Toshiaki Iwamatsu ,  Shigenobu Maeda ,  Il-Jung Kim ,  Kazuhito Tsutsumi ,  Hirotada Kuriyama ,  Yoshiyuki Ishigaki ,  Motomu Ukita ,  Toshiaki Tsutsumi

IPC分类号： H01L31/00

CPC分类号： H01L29/78609 ,  H01L27/124 ,  H01L29/41733 ,  H01L29/458 ,  H01L29/66757 ,  H01L29/78618 ,  H01L29/78624 ,  H01L29/78639

摘要： Provided are a thin-film transistor formed by connecting polysilicon layers having different conductivity types with each other which prevents occurrence of inconvenience resulting from diffusion of impurities and a method of fabricating the same. A drain (6), a channel (7) and a source (8) are integrally formed on a surface of a second oxide film (4) by polysilicon. The drain (6) is formed to be connected with a pad layer (3) (second polycrystalline semiconductor layer) through a contact hole (5) which is formed to reach an upper surface of the pad layer (3). The pad layer (3) positioned on a bottom portion of the contact hole (5) (opening) is provided with a boron implantation region BR.

公开(公告)号：US20060134843A1

公开(公告)日：2006-06-22

申请号：US11317687

申请日：2005-12-27

申请人： Shigenobu Maeda ,  Takuji Matsumoto ,  Toshiaki Iwamatsu ,  Takashi Ipposhi

发明人： Shigenobu Maeda ,  Takuji Matsumoto ,  Toshiaki Iwamatsu ,  Takashi Ipposhi

IPC分类号： H01L21/336

CPC分类号： H01L29/66772 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/42368 ,  H01L29/4238 ,  H01L29/42384 ,  H01L29/7841 ,  H01L29/78615 ,  H01L29/78654 ,  Y10S438/981

摘要： It is an object to provide an SOI device capable of carrying out body fixation and implementing a quick and stable operation. A gate insulating film (11) having a thickness of 1 to 5 nm is provided between a portion other than a gate contact pad (GP) of a gate electrode (12) and an SOI layer (3), and a gate insulating film (110) having a thickness of 5 to 15 nm is provided between the gate contact pad (GP) and the SOI layer (3). The gate insulating film (11) and the gate insulating film (110) are provided continuously.

摘要翻译： 本发明的目的是提供一种能够进行身体固定并实现快速且稳定的操作的SOI装置。 在栅极（12）的栅极接触焊盘（GP）与SOI层（3）之间的部分之间设置厚度为1〜5nm的栅极绝缘膜（11）和栅极绝缘膜（ 在栅极接触焊盘（GP）和SOI层（3）之间设置有厚度为5〜15nm的光栅（110）。 连续设置栅极绝缘膜（11）和栅极绝缘膜（110）。

公开(公告)号：US20050275021A1

公开(公告)日：2005-12-15

申请号：US11197397

申请日：2005-08-05

申请人： Takuji Matsumoto ,  Takashi Ipposhi ,  Toshiaki Iwamatsu ,  Yuuichi Hirano

发明人： Takuji Matsumoto ,  Takashi Ipposhi ,  Toshiaki Iwamatsu ,  Yuuichi Hirano

IPC分类号： H01L21/762 ,  H01L21/336 ,  H01L21/76 ,  H01L21/8234 ,  H01L21/8238 ,  H01L21/84 ,  H01L27/01 ,  H01L27/08 ,  H01L27/088 ,  H01L27/092 ,  H01L27/12 ,  H01L29/78 ,  H01L29/786

CPC分类号： H01L29/66545 ,  H01L21/28052 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/41766 ,  H01L29/4933 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7834 ,  H01L29/7845

摘要： A semiconductor device and its manufacturing method are provided which can properly avoid reduction of isolation breakdown voltage without involving adverse effects like an increase in junction capacitance. Impurity-introduced regions (11) are formed after a silicon layer (3) has been thinned through formation of recesses (14). Therefore n-type impurities are not implanted into the portions of the p-type silicon layer (3) that are located between the bottoms of element isolation insulating films (5) and the top surface of a BOX layer (2), which avoids reduction of isolation breakdown voltage. Furthermore, since the impurity-introduced regions (11) are formed to reach the upper surface of the BOX layer (2), the junction capacitance of source/drain regions (12) is not increased.

摘要翻译： 提供一种半导体器件及其制造方法，其可以适当地避免隔离击穿电压的降低，而不会引起诸如结电容增加的不利影响。 在通过形成凹部（14）使硅层（3）变薄之后形成杂质导入区域（11）。 因此，在位于元件隔离绝缘膜（5）的底部和BOX层（2）的上表面之间的p型硅层（3）的部分中不会注入n型杂质，避免了还原 的隔离击穿电压。 此外，由于杂质引入区域（11）形成为到达BOX层（2）的上表面，所以源极/漏极区域（12）的结电容不增加。

公开(公告)号：US20050133864A1

公开(公告)日：2005-06-23

申请号：US11002142

申请日：2004-12-03

申请人： Toshiaki Iwamatsu ,  Takashi Ipposhi

发明人： Toshiaki Iwamatsu ,  Takashi Ipposhi

IPC分类号： H01L21/76 ,  H01L21/762 ,  H01L21/822 ,  H01L21/8234 ,  H01L21/84 ,  H01L27/04 ,  H01L27/06 ,  H01L27/08 ,  H01L27/12 ,  H01L27/13 ,  H01L29/786 ,  H01L21/00 ,  H01L27/01 ,  H01L31/0392

CPC分类号： H01L27/0617 ,  H01L21/76283 ,  H01L21/84 ,  H01L27/0629 ,  H01L27/1203 ,  H01L27/13 ,  H01L28/10 ,  H01L28/20 ,  H01L29/665 ,  H01L29/6659 ,  H01L29/7833

摘要： Plural trench isolation films (4) are provided with portions of an SOI layer (3) interposed therebetween in a surface of the SOI layer (3) in a resistor region (RR) where a spiral inductor (SI) is to be provided. Resistive element (30) are formed on the trench isolation films (4), respectively. Each of the trench isolation films (4) includes a central portion which passes through the SOI layer (3) and reaches a buried oxide film (2) to include a full-trench isolation structure, and opposite side portions each of which passes through only a portion of the SOI layer (3) and is located on the SOI layer 3 to include a partial-trench isolation structure. Thus, each of the trench isolation films (4) includes a hybrid-trench isolation structure.

摘要翻译： 多个沟槽隔离膜（4）在其中设置有螺旋电感器（SI）的电阻器区域（RR）中的SOI层（3）的表面中设置有SOI层（3）的部分。 电阻元件（30）分别形成在沟槽隔离膜（4）上。 每个沟槽隔离膜（4）包括通过SOI层（3）并到达掩埋氧化膜（2）以包括全沟槽隔离结构的中心部分，并且每个沟道隔离膜仅穿过 SOI层（3）的一部分并且位于SOI层3上以包括部分沟槽隔离结构。 因此，每个沟槽隔离膜（4）包括混合沟槽隔离结构。