公开(公告)号：US07679744B2

公开(公告)日：2010-03-16

申请号：US11987714

申请日：2007-12-04

Applicant: Mieko Yamagaki ,  Yu Mimura ,  Kazuyou Mizuno ,  Takeshi Takagi

Inventor： Mieko Yamagaki ,  Yu Mimura ,  Kazuyou Mizuno ,  Takeshi Takagi

IPC: G01J4/00

CPC classification number: G01J4/00

Abstract: The invention provides a Stokes parameter measurement device and Stokes parameter measurement method that enable high-precision measurement. The Stokes parameter measurement device comprises a polarization splitting device which comprises an optical element formed of a birefringent crystal material and which, by means of the optical element, splits signal light to be measured into a plurality of polarized light beams and adjusts the polarization state of one or more among the plurality of polarized light beams, and a light-receiving portion for performing photoelectric conversion of an optical component of the signal light split by and emitted from the polarization splitting device.

Abstract translation: 本发明提供了能够进行高精度测量的斯托克斯参数测量装置和斯托克斯参数测量方法。 斯托克斯参数测量装置包括偏振分离装置，其包括由双折射晶体材料形成的光学元件，并且通过光学元件将待测量的信号光分解为多个偏振光束并调节偏振态 多个偏振光束中的一个或多个，以及用于对由偏振分离装置分离和发射的信号光的光学分量执行光电转换的光接收部分。

公开(公告)号：US20100051892A1

公开(公告)日：2010-03-04

申请号：US12446964

申请日：2007-10-22

Applicant: Takumi Mikawa ,  Takeshi Takagi

Inventor： Takumi Mikawa ,  Takeshi Takagi

IPC: H01L47/00 ,  H01L21/16

CPC classification number: H01L27/101 ,  H01L27/24

Abstract: A nonvolatile semiconductor memory apparatus (10) of the present invention comprises a semiconductor substrate (11), an active element forming region provided on the semiconductor substrate (11) and including a plurality of active elements (12), a wire forming region which is provided on the active element forming region to electrically connect the active elements (12) and includes plural layers of semiconductor electrode wires (15, 16), a memory portion forming region (100) which is provided above the wire forming region and provided with memory portions (26) arranged in matrix, a resistance value of each of the memory portions changing according to electric pulses applied, and an oxygen barrier layer (17) which is provided between the memory portion forming region (100) and the wire forming region so as to extend continuously over at least an entire of the memory portion forming region (100).

Abstract translation: 本发明的非易失性半导体存储器件（10）包括半导体衬底（11），设置在半导体衬底（11）上并包括多个有源元件（12）的有源元件形成区域， 设置在有源元件形成区域上以电连接有源元件（12）并且包括多层半导体电极线（15,16），存储部形成区域（100），其设置在线形成区域的上方并设置有存储器 布置成矩阵的部分（26），每个存储部分的电阻值根据施加的电脉冲而变化，以及设置在存储部分形成区域（100）和线形成区域之间的氧阻挡层（17），从而 以在至少整个存储部分形成区域（100）上连续地延伸。

公开(公告)号：US20090283736A1

公开(公告)日：2009-11-19

申请号：US12307211

申请日：2008-03-26

Applicant: Yoshihiko Kanzawa ,  Koji Katayama ,  Satoru Fujii ,  Shunsaku Muraoka ,  Koichi Osano ,  Satoru Mitani ,  Ryoko Miyanaga ,  Takeshi Takagi ,  Kazuhlko Shimakawa

Inventor： Yoshihiko Kanzawa ,  Koji Katayama ,  Satoru Fujii ,  Shunsaku Muraoka ,  Koichi Osano ,  Satoru Mitani ,  Ryoko Miyanaga ,  Takeshi Takagi ,  Kazuhlko Shimakawa

IPC: H01L45/00 ,  H01L21/16 ,  H01L29/12

CPC classification number: H01L27/101 ,  G11C13/0007 ,  G11C13/004 ,  G11C13/0069 ,  G11C2013/0073 ,  G11C2213/32 ,  G11C2213/71 ,  G11C2213/72 ,  G11C2213/79 ,  H01L27/2409 ,  H01L27/2436 ,  H01L27/2481 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/1625 ,  H01L45/1675 ,  Y10S438/90

Abstract: A nonvolatile memory element comprises a first electrode layer (103), a second electrode (107), and a resistance variable layer (106) which is disposed between the first electrode layer (103) and the second electrode layer (107), a resistance value of the resistance variable layer varying reversibly according to electric signals having different polarities which are applied between the electrodes (103), (107), wherein the resistance variable layer (106) has a first region comprising a first oxygen-deficient tantalum oxide having a composition represented by TaOx (0

Abstract translation: 非易失性存储元件包括设置在第一电极层（103）和第二电极层（107）之间的第一电极层（103），第二电极（107）和电阻变化层（106），电阻 电阻变化层的值根据施加在电极（103），（107）之间的具有不同极性的电信号而可逆地变化，其中电阻变化层（106）具有第一区域，该第一区域包括第一氧缺陷型氧化钽， 由TaOx（0

公开(公告)号：US07586130B2

公开(公告)日：2009-09-08

申请号：US11344574

申请日：2006-02-01

Applicant: Takahiro Kawashima ,  Tohru Saitoh ,  Takeshi Takagi

Inventor： Takahiro Kawashima ,  Tohru Saitoh ,  Takeshi Takagi

IPC: H01L29/732

CPC classification number: H01L29/78696 ,  B82Y10/00 ,  H01L29/0665 ,  H01L29/0673 ,  H01L29/0676 ,  H01L29/1606 ,  H01L29/42384 ,  H01L29/7781 ,  H01L29/78642 ,  Y10S977/938

Abstract: A vertical field effect transistor includes: an active region with a bundle of linear structures functioning as a channel region; a lower electrode, functioning as one of source and drain regions; an upper electrode, functioning as the other of the source and drain regions; a gate electrode for controlling the electric conductivity of at least a portion of the bundle of linear structures included in the active region; and a gate insulating film arranged between the active region and the gate electrode to electrically isolate the gate electrode from the bundle of linear structures. The transistor further includes a dielectric portion between the upper and lower electrodes. The upper electrode is located over the lower electrode with the dielectric portion interposed and includes an overhanging portion sticking out laterally from over the dielectric portion. The active region is located right under the overhanging portion of the upper electrode.

Abstract translation: 垂直场效应晶体管包括：具有用作沟道区的线性结构束的有源区; 用作源极和漏极区之一的下电极; 上电极，用作源极和漏极区域中的另一个; 用于控制所述有源区域中包括的所述线性结构束的至少一部分的电导率的栅电极; 以及栅极绝缘膜，其布置在所述有源区和所述栅电极之间，以将所述栅电极与所述线结构的束电隔离。 晶体管还包括在上电极和下电极之间的电介质部分。 上电极位于下电极的上方，电介质部分插入，并且包括从电介质部分的上方横向突出的突出部分。 有源区域位于上电极的伸出部分正下方。

公开(公告)号：US07564073B2

公开(公告)日：2009-07-21

申请号：US11294566

申请日：2005-12-06

Applicant: Haruyuki Sorada ,  Akira Asai ,  Takeshi Takagi ,  Akira Inoue ,  Yoshio Kawashima

Inventor： Haruyuki Sorada ,  Akira Asai ,  Takeshi Takagi ,  Akira Inoue ,  Yoshio Kawashima

IPC: H01L27/04

CPC classification number: H01L21/823807

Abstract: A semiconductor integrated circuit fabrication method according to this invention includes: a step of forming a pair of first device forming regions and a pair of second device forming regions in a surface layer portion of a semiconductor substrate by surrounding each of the regions by device isolation; a step of forming a first oxide film covering the surface of the semiconductor substrate after the preceding step; a step of removing an intended portion of the first oxide film to expose the pair of second device forming regions; a step of forming a pair of heterojunction structures, by selective epitaxial growth, on the pair of second device forming regions thus exposed; a step of forming a second oxide film covering the surface of the substrate after the preceding step; and a step of forming a pair of gate electrodes above each of the pair of first device forming regions and the pair of second device forming regions, whereby a normal complementary MOS transistor and a heterojunction complementary MOS transistor are eventually formed in the pair of first device forming regions and the pair of second device forming regions, respectively.

Abstract translation: 根据本发明的半导体集成电路制造方法包括：通过器件隔离来围绕每个区域来在半导体衬底的表面层部分中形成一对第一器件形成区域和一对第二器件形成区域的步骤; 在前述步骤之后形成覆盖半导体衬底的表面的第一氧化物膜的步骤; 去除所述第一氧化物膜的预期部分以暴露所述一对第二器件形成区域的步骤; 通过选择性外延生长形成一对异质结结构在由此露出的一对第二器件形成区上的步骤; 在上述步骤之后形成覆盖基板表面的第二氧化膜的步骤; 以及在所述一对第一器件形成区域和所述一对第二器件形成区域中的每一个上形成一对栅电极的步骤，由此在所述一对第一器件形成区域中最终形成正常互补MOS晶体管和异质结互补MOS晶体管 形成区域和一对第二装置形成区域。

公开(公告)号：US20070052041A1

公开(公告)日：2007-03-08

申请号：US10558671

申请日：2004-05-31

Applicant: Haruyuki Sorada ,  Takeshi Takagi ,  Akira Asai ,  Yoshihiko Kanzawa ,  Kouji Katayama ,  Junko Iwanaga

Inventor： Haruyuki Sorada ,  Takeshi Takagi ,  Akira Asai ,  Yoshihiko Kanzawa ,  Kouji Katayama ,  Junko Iwanaga

IPC: H01L29/94

CPC classification number: H01L29/785 ,  H01L29/66795 ,  H01L29/78687

Abstract: A semiconductor device according to this invention includes: a first insulating layer (11); a first body section (13) including an island-shaped semiconductor formed on the first insulating layer; a second body section (14) including an island-shaped semiconductor formed on the first insulating layer; a ridge-shaped connecting section (15) formed on the first insulating layer to interconnect the first body section and the second body section; a channel region (15a) formed by at least a part of the connecting section in lengthwise direction of the connecting section; a gate electrode (18) formed to cover a periphery of the channel region, with a second insulating layer intervening therebetween; a source region formed to extend over the first body section and a portion of the connecting section between the first body section and the channel region; and a drain region formed to extend over the second body section and a portion of the connecting section between the second body section and the channel region, wherein a semiconductor forming the channel region has a lattice strain.

Abstract translation: 根据本发明的半导体器件包括：第一绝缘层（11）; 第一主体部分（13），其包括形成在所述第一绝缘层上的岛状半导体; 包括形成在所述第一绝缘层上的岛状半导体的第二主体部分（14） 形成在第一绝缘层上以互连第一主体部分和第二主体部分的脊形连接部分（15）; 由所述连接部的至少一部分在所述连接部的长度方向上形成的通路区域（15a） 形成为覆盖沟道区域的周边的栅极电极（18），其间插入有第二绝缘层; 形成为在第一主体部分上延伸的源极区域和在第一主体部分和沟道区域之间的连接部分的一部分; 以及形成为在第二主体部分上延伸的漏极区域和在第二主体部分和沟道区域之间的连接部分的一部分，其中形成沟道区域的半导体具有晶格应变。

公开(公告)号：US07084026B2

公开(公告)日：2006-08-01

申请号：US10913383

申请日：2004-08-09

Applicant: Takeshi Takagi ,  Akira Inoue

Inventor： Takeshi Takagi ,  Akira Inoue

IPC: H01L21/8238 ,  H01L21/336

CPC classification number: H01L29/802 ,  H01L21/823807 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/78687

Abstract: A region of an Si layer 15 located between source and drain regions 19 and 20 is an Si body region 21 which contains an n-type impurity of high concentration. An Si layer 16 and an SiGe layer 17 are, in an as grown state, undoped layers into which no n-type impurity is doped. Regions of the Si layer 16 and the SiGe layer 17 located between the source and drain regions 19 and 20 are an Si buffer region 22 and an SiGe channel region 23, respectively, which contain the n-type impurity of low concentration. A region of an Si film 18 located directly under a gate insulating film 12 is an Si cap region 24 into which a p-type impurity (5×1017 atoms·cm−3) is doped. Accordingly, a semiconductor device in which an increase in threshold voltage is suppressed can be achieved.

Abstract translation: 位于源区和漏区19和20之间的Si层15的区域是含有高浓度的n型杂质的Si体区21。 处于生长状态的Si层16和SiGe层17未掺杂n型杂质的未掺杂层。 位于源区和漏区19和20之间的Si层16和SiGe层17的区域分别是含有低浓度的n型杂质的Si缓冲区22和SiGe沟道区23。 位于栅极绝缘膜12正下方的Si膜18的区域是Si帽区域24，其中p型杂质（5×10 17原子％-3重量％ ）掺杂。 因此，可以实现抑制阈值电压增加的半导体装置。

公开(公告)号：US20060054944A1

公开(公告)日：2006-03-16

申请号：US11260197

申请日：2005-10-28

Applicant: Haruyuki Sorada ,  Takeshi Takagi ,  Akira Asai ,  Akira Inoue

Inventor： Haruyuki Sorada ,  Takeshi Takagi ,  Akira Asai ,  Akira Inoue

IPC: H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC classification number: H01L29/78696 ,  H01L21/76264 ,  H01L21/76281 ,  H01L29/1054 ,  H01L29/66742 ,  H01L29/78687 ,  Y10S438/933 ,  Y10S438/938

Abstract: The present invention provides a semiconductor device comprising: a semiconductor layer (3); a gate electrode (11) formed on the semiconductor layer (3) via a gate insulation film (10); and a first insulation film (13) formed at one or more of sidewalls of the semiconductor layer (3), the gate insulation film (10) and the gate electrode (11); wherein the first insulation film (13) overlies a part of the gate insulation film (10) surface. According to the semiconductor device, leakage current at the isolation edge can be suppressed and thus reliability can be improved.

Abstract translation: 本发明提供一种半导体器件，包括：半导体层（3）; 经由栅极绝缘膜（10）形成在所述半导体层（3）上的栅电极（11）; 以及形成在所述半导体层（3），所述栅极绝缘膜（10）和所述栅电极（11）的侧壁的一个或多个的第一绝缘膜（13）。 其中所述第一绝缘膜（13）覆盖所述栅极绝缘膜（10）表面的一部分。 根据半导体装置，可以抑制隔离边缘处的漏电流，从而可以提高可靠性。

公开(公告)号：US20050093020A1

公开(公告)日：2005-05-05

申请号：US10983610

申请日：2004-11-09

Applicant: Akira Inoue ,  Takeshi Takagi ,  Yoshihiro Hara ,  Minoru Kubo

Inventor： Akira Inoue ,  Takeshi Takagi ,  Yoshihiro Hara ,  Minoru Kubo

IPC: H01L21/02 ,  H01L21/314 ,  H01L21/316 ,  H01L21/77 ,  H01L21/8238 ,  H01L21/8242 ,  H01L21/8246 ,  H01L21/84 ,  H01L27/092 ,  H01L27/115 ,  H01L27/12 ,  H01L29/10 ,  H01L29/78 ,  H01L29/786 ,  H01L29/80 ,  H01L31/0392

CPC classification number: H01L29/802 ,  H01L21/823807 ,  H01L21/84 ,  H01L27/092 ,  H01L27/10873 ,  H01L27/11502 ,  H01L27/11507 ,  H01L27/1203 ,  H01L27/1214 ,  H01L27/1222 ,  H01L28/55 ,  H01L29/1054 ,  H01L29/783 ,  H01L29/78687

Abstract: A silicon oxide film 102, a Pt film 103x, a Ti film 104x and a PZT film 105x are deposited in this order over a Si substrate 101. The Si substrate 101 is placed in a chamber 106 so that the PZT film 105x is irradiated with an EHF wave 108. The irradiation with the EHF wave locally heats a dielectric film such as the PZT film. As a result, it is possible to improve, for example, the leakage property of the dielectric film without adversely affecting a device formed on the Si substrate 101.

Abstract translation: 依次沉积硅衬底101上的氧化硅膜102，Pt膜103x，Ti膜104x和PZT膜105x。 将Si衬底101放置在室106中，使得PZT膜105x被EHF波108照射。 用EHF波照射局部加热电介质膜，例如PZT膜。 结果，可以改善例如电介质膜的泄漏特性，而不会对形成在Si衬底101上的器件产生不利影响。

公开(公告)号：US06858454B1

公开(公告)日：2005-02-22

申请号：US10674523

申请日：2003-10-01

Applicant: Yoshihiko Kanzawa ,  Tohru Saitoh ,  Takeshi Takagi ,  Katsuya Nozawa

Inventor： Yoshihiko Kanzawa ,  Tohru Saitoh ,  Takeshi Takagi ,  Katsuya Nozawa

IPC: G01N21/21 ,  G01N21/35 ,  H01L21/66

CPC classification number: G01N21/3563 ,  G01N21/211

Abstract: A method for measuring semiconductor constituent element content utilizes the steps of: obtaining a film thickness of an SiGeC layer formed on a semiconductor substrate by evaluation using spectroscopic ellipsometry; measuring infrared absorption spectrum of the SiGeC layer; and obtaining a C content of the SiGeC layer based on the film thickness and the infrared absorption spectrum of the SiGeC layer. The method: obtaining an apparent Ge content of the SiGeC layer by evaluation using spectroscopic ellipsometry; and obtaining an actual Ge content of the SiGeC layer based on the apparent Ge content and the C content. The constituent element content of the SiGeC layer can be easily and accurately measured according to the above-mentioned method.

Abstract translation: 一种测量半导体构成元件含量的方法采用以下步骤：通过使用分光椭圆偏光度法评估在半导体衬底上形成的SiGeC层的膜厚度; 测量SiGeC层的红外吸收光谱; 并根据SiGeC层的膜厚和红外吸收光谱获得SiGeC层的C含量。 该方法：通过使用分光椭偏仪评估获得SiGeC层的表观Ge含量; 并且基于表观Ge含量和C含量获得SiGeC层的实际Ge含量。 根据上述方法可以容易且精确地测量SiGeC层的构成元素含量。