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    Vector reverse
    61.
    发明授权
    Vector reverse 有权

    公开(公告)号：US11288067B2

    公开(公告)日：2022-03-29

    申请号：US16422795

    申请日：2019-05-24

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Timothy D. Anderson ,  Duc Bui

    IPC: G06F9/30

    Abstract: A method to reverse source data in a processor in response to a vector reverse instruction includes specifying, in respective fields of the vector reverse instruction, a source register containing the source data and a destination register. The source register includes a plurality of lanes and each lane contains a data element, and the destination register includes a plurality of lanes corresponding to the lanes of the source register. The method further includes executing the vector reverse instruction by creating reversed source data by reversing the order of the data elements, and storing the reversed source data in the destination register.

    Variable latency instructions
    62.
    发明授权
    Variable latency instructions 有权

    公开(公告)号：US11210098B2

    公开(公告)日：2021-12-28

    申请号：US16384328

    申请日：2019-04-15

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Timothy D. Anderson

    IPC: G06F9/312 ,  G06F9/38 ,  G06F11/00 ,  G06F12/0875 ,  G06F9/30 ,  G06F11/10 ,  G06F9/32 ,  G06F12/0897 ,  G06F9/345

    Abstract: Techniques related to executing instructions by a processor comprising receiving a first instruction for execution, determining a first latency value based on an expected amount of time needed for the first instruction to be executed, storing the first latency value in a writeback queue, beginning execution of the first instruction on the instruction execution pipeline, adjusting the latency value based on an amount of time passed since beginning execution of the first instruction, outputting a first result of the first instruction based on the latency value, receiving a second instruction, determining that the second instruction is a variable latency instruction, storing a ready value indicating that a second result of the second instruction is not ready in the writeback queue, beginning execution of the second instruction on the instruction execution pipeline, updating the ready value to indicate that the second result is ready, and outputting the second result.

    NESTED LOOP CONTROL
    63.
    发明申请
    NESTED LOOP CONTROL 有权

    公开(公告)号：US20210334103A1

    公开(公告)日：2021-10-28

    申请号：US17367384

    申请日：2021-07-04

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Kai Chirca ,  Timothy D. Anderson ,  Todd T. Hahn ,  Alan L. Davis

    IPC: G06F9/30

    Abstract: A nested loop controller includes a first register having a first value initialized to an initial first value, a second register having a second value initialized to an initial second value, and a third register configured as a predicate FIFO, initialized to have a third value. The second value is advanced in response to a tick instruction during execution of a loop. In response to the second value reaching a second threshold, the second register is reset to the initial second value. The nested loop controller further includes a comparator coupled to the second register and to the predicate FIFO and configured to provide an outer loop indicator value as input to the predicate FIFO when the second value is equal to the second threshold, and provide an inner loop indicator value as input to the predicate FIFO when the second value is not equal to the second threshold.

    Vector maximum and minimum with indexing
    66.
    发明授权
    Vector maximum and minimum with indexing 有权

    公开(公告)号：US10963252B2

    公开(公告)日：2021-03-30

    申请号：US16422501

    申请日：2019-05-24

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Duc Bui ,  Peter Richard Dent ,  Timothy D. Anderson

    IPC: G06F9/30

    Abstract: A method to compare first and second source data in a processor in response to a vector maximum with indexing instruction includes specifying first and second source registers containing first and second source data, a destination register storing compared data, and a predicate register. Each of the registers includes a plurality of lanes. The method includes executing the instruction by, for each lane in the first and second source register, comparing a value in the lane of the first source register to a value in the corresponding lane of the second source register to identify a maximum value, storing the maximum value in a corresponding lane of the destination register, asserting a corresponding lane of the predicate register if the maximum value is from the first source register, and de-asserting the corresponding lane of the predicate register if the maximum value is from the second source register.

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