公开(公告)号：US5831301A

公开(公告)日：1998-11-03

申请号：US14523

申请日：1998-01-28

申请人： David Vaclav Horak ,  Toshiharu Furukawa ,  Steven John Holmes ,  Mark Charles Hakey ,  William Hsioh-Lien Ma ,  Jack Allan Mandelman

发明人： David Vaclav Horak ,  Toshiharu Furukawa ,  Steven John Holmes ,  Mark Charles Hakey ,  William Hsioh-Lien Ma ,  Jack Allan Mandelman

IPC分类号： H01L21/76 ,  H01L21/8242 ,  H01L27/108 ,  H01L29/76

CPC分类号： H01L27/10864 ,  H01L27/10841

摘要： A memory cell including a substrate, at least one deep trench capacitor in the substrate, at least one FET in the substrate disposed over at least a portion of the at least one deep trench capacitor, and at least one isolation region in the substrate surrounding the at least one FET and having a greater depth than the at least one FET. The at least one FET includes a gate disposed over at least a portion of the at least one deep trench capacitor and doped regions arranged on adjacent sides of the gate and separated from the gate by an insulating layer.

摘要翻译： 存储单元，包括衬底，衬底中的至少一个深沟槽电容器，设置在所述至少一个深沟槽电容器的至少一部分上的所述衬底中的至少一个FET以及所述衬底中的至少一个隔离区域， 至少一个FET并且具有比所述至少一个FET更大的深度。 所述至少一个FET包括设置在所述至少一个深沟槽电容器的至少一部分上的栅极和布置在栅极的相邻侧上的掺杂区域，并且通过绝缘层与栅极分离。

公开(公告)号：US07027125B2

公开(公告)日：2006-04-11

申请号：US10808740

申请日：2004-03-25

申请人： Mark Charles Hakey ,  David Vaclay Horak ,  Charles William Koburger, III ,  Peter H. Mitchell

发明人： Mark Charles Hakey ,  David Vaclay Horak ,  Charles William Koburger, III ,  Peter H. Mitchell

IPC分类号： G03B27/52 ,  G03B27/42

CPC分类号： G03F7/70808 ,  G03F7/70341

摘要： A photolithographic apparatus, system and method employing an improved refractive medium. The photolithographic apparatus may be used in an immersion lithography system for projecting light onto a workpiece such as a semiconductor wafer. In one embodiment, the photolithographic apparatus includes a container containing a transparent fluid. The fluid container is positioned between a lens element and the wafer. The container is further characterized as having a substantially flexible and transparent bottom membrane contacting an upper surface of the wafer and overlapping at least one side edge of the wafer such that a fluid filled skirt is formed extending beyond the edges of the wafer.

摘要翻译： 一种使用改进的折射介质的光刻设备，系统和方法。 光刻设备可以用于浸入式光刻系统中，用于将光投射到诸如半导体晶片的工件上。 在一个实施例中，光刻设备包括容纳透明流体的容器。 流体容器位于透镜元件和晶片之间。 该容器的特征还在于具有与晶片的上表面接触并且与晶片的至少一个侧边缘重叠的基本柔性且透明的底膜，从而形成延伸超过晶片边缘的充满液体的裙部。

公开(公告)号：US06441464B1

公开(公告)日：2002-08-27

申请号：US09401054

申请日：1999-09-22

申请人： Steven J. Holmes ,  Mark Charles Hakey ,  Toshiharu Furukawa ,  David Vaclav Horak

发明人： Steven J. Holmes ,  Mark Charles Hakey ,  Toshiharu Furukawa ,  David Vaclav Horak

IPC分类号： H01L31117

CPC分类号： H01L21/28194 ,  H01L21/28026 ,  H01L21/28035 ,  H01L21/2807 ,  H01L29/49 ,  H01L29/4975 ,  H01L29/517 ,  H01L29/518 ,  Y10S438/933

摘要： A semi-conductor device includes a silicon substrate. A gate oxide dielectric layer is on the silicon substrate. A gate conductor includes a relatively thin layer of germanium on the dielectric layer. A relatively thick layer of gate conductor material is provided on the layer of germanium. Incorporating germanium at the gate conductor interface with the gate oxide stabilizes the gate oxide by providing a means of drawing charge trapping sites away from the oxide.

公开(公告)号：US20080258181A1

公开(公告)日：2008-10-23

申请号：US11737989

申请日：2007-04-20

申请人： Ethan Harrison Cannon ,  Toshiharu Furukawa ,  John Gerard Gaudiello ,  Mark Charles Hakey ,  Steven John Holmes ,  David Vaclav Horak ,  Charles William Koburger ,  Jack Allan Mandelman ,  William Robert Tonti

发明人： Ethan Harrison Cannon ,  Toshiharu Furukawa ,  John Gerard Gaudiello ,  Mark Charles Hakey ,  Steven John Holmes ,  David Vaclav Horak ,  Charles William Koburger ,  Jack Allan Mandelman ,  William Robert Tonti

IPC分类号： H01L27/092 ,  H01L21/8238

CPC分类号： H01L21/76243 ,  H01L21/76251 ,  H01L21/823807 ,  H01L21/823878 ,  H01L21/84 ,  H01L27/1203 ,  H01L27/1207

摘要： Hybrid substrates characterized by semiconductor islands of different crystal orientations and methods of forming such hybrid substrates. The methods involve using a SIMOX process to form an insulating layer. The insulating layer may divide the islands of at least one of the different crystal orientations into mutually aligned device and body regions. The body regions may be electrically floating relative to the device regions.

摘要翻译： 以不同晶体取向的半导体岛为特征的混合基板和形成这种混合基板的方法。 该方法涉及使用SIMOX工艺来形成绝缘层。 绝缘层可以将不同晶体取向中的至少一个的岛分成相互排列的器件和体区。 身体区域可以相对于装置区域电浮动。

公开(公告)号：US06583462B1

公开(公告)日：2003-06-24

申请号：US09702338

申请日：2000-10-31

申请人： Toshiharu Furukawa ,  Rajarao Jammy ,  Thomas Kanarsky ,  Jeffrey John Welser ,  David Vaclav Horak ,  Steven John Holmes ,  Mark Charles Hakey

发明人： Toshiharu Furukawa ,  Rajarao Jammy ,  Thomas Kanarsky ,  Jeffrey John Welser ,  David Vaclav Horak ,  Steven John Holmes ,  Mark Charles Hakey

IPC分类号： H01L27108

CPC分类号： H01L27/10864 ,  H01L27/10841 ,  H01L27/10867

摘要： A dynamic random access memory device formed in a substrate having a trench. The trench has a side wall, a top, a lower portion, and a circumference. The device includes a signal storage node including a metallic storage node conductor formed in the lower portion of the trench and isolated from the side wall by a node dielectric and a collar oxide above the node dielectric. Preferably, the trench has an aspect ratio of greater than 50. A buried strap is coupled to the storage node conductor and contacts a portion of the side wall of the trench above the collar oxide. A trench-top dielectric which is formed upon the buried strap has a trench-top dielectric thickness. A signal transfer device includes a first diffusion region extending into the substrate adjacent the portion of the trench side wall contacted by the buried strap, a gate insulator having a gate insulator thickness formed on the trench side wall above the first buried strap, wherein the gate insulator thickness is less than the trench-top dielectric thickness, and a gate conductor formed within the trench upon the trench-top dielectric and adjacent the gate insulator.

摘要翻译： 形成在具有沟槽的衬底中的动态随机存取存储器件。 沟槽具有侧壁，顶部，下部和圆周。 该装置包括信号存储节点，该信号存储节点包括形成在沟槽下部的金属存储节点导体，并通过节点电介质和节点电介质上方的环形氧化物与侧壁隔离。 优选地，沟槽具有大于50的纵横比。掩埋带耦合到存储节点导体并且接触环形氧化物上方的沟槽的侧壁的一部分。 形成在掩埋带上的沟槽电介质具有沟槽顶部的电介质厚度。 信号传送装置包括：第一扩散区域，其延伸到与所述掩埋带接触的所述沟槽侧壁的所述部分相邻的所述衬底;门绝缘体，其具有形成在所述第一掩埋带的上方的所述沟槽侧壁上的栅绝缘体厚度， 绝缘体厚度小于沟槽顶部电介质厚度，以及形成在沟槽顶部电介质并且邻近栅极绝缘体的沟槽内的栅极导体。

公开(公告)号：US6063658A

公开(公告)日：2000-05-16

申请号：US172865

申请日：1998-10-15

申请人： David Vaclav Horak ,  Toshiharu Furukawa ,  Steven John Holmes ,  Mark Charles Hakey ,  William Hsioh-Lien Ma ,  Jack Allan Mandelman

发明人： David Vaclav Horak ,  Toshiharu Furukawa ,  Steven John Holmes ,  Mark Charles Hakey ,  William Hsioh-Lien Ma ,  Jack Allan Mandelman

IPC分类号： H01L21/76 ,  H01L21/8242 ,  H01L27/108

CPC分类号： H01L27/10864 ,  H01L27/10841

摘要： A memory cell including a substrate, at least one deep trench capacitor in the substrate, at least one FET in the substrate disposed over at least a portion of the at least one deep trench capacitor, and at least one isolation region in the substrate surrounding the at least one FET and having a greater depth than the at least one FET. The at least one FET includes a gate disposed over at least a portion of the at least one deep trench capacitor and doped regions arranged on adjacent sides of the gate and separated from the gate by an insulating layer.

摘要翻译： 存储单元，包括衬底，衬底中的至少一个深沟槽电容器，设置在所述至少一个深沟槽电容器的至少一部分上的所述衬底中的至少一个FET以及所述衬底中的至少一个隔离区域， 至少一个FET并且具有比所述至少一个FET更大的深度。 所述至少一个FET包括设置在所述至少一个深沟槽电容器的至少一部分上的栅极和布置在栅极的相邻侧上的掺杂区域，并且通过绝缘层与栅极分离。

公开(公告)号：US20080258222A1

公开(公告)日：2008-10-23

申请号：US11877871

申请日：2007-10-24

申请人： Ethan Harrison Cannon ,  Toshiharu Furukawa ,  John Gerard Gaudiello ,  Mark Charles Hakey ,  Steven John Holmes ,  David Vaclav Horak ,  Charles William Koburger ,  Jack Allan Mandelman ,  William Robert Tonti

发明人： Ethan Harrison Cannon ,  Toshiharu Furukawa ,  John Gerard Gaudiello ,  Mark Charles Hakey ,  Steven John Holmes ,  David Vaclav Horak ,  Charles William Koburger ,  Jack Allan Mandelman ,  William Robert Tonti

IPC分类号： H01L27/12

CPC分类号： H01L21/76264

摘要： Design structure embodied in a machine readable medium for designing, manufacturing, or testing a design in which the design structure includes devices formed in a hybrid substrate characterized by semiconductor islands of different crystal orientations. An insulating layer divides the islands of at least one of the different crystal orientations into mutually aligned device and body regions. The body regions may be electrically floating relative to the device regions.

摘要翻译： 设计结构体现在机器可读介质中，用于设计，制造或测试设计，其中设计结构包括以混合衬底形成的器件，其特征在于具有不同晶体取向的半导体岛。 绝缘层将至少一个不同晶体取向的岛分成相互排列的器件和体区。 身体区域可以相对于装置区域电浮动。

公开(公告)号：US20080166863A1

公开(公告)日：2008-07-10

申请号：US12052855

申请日：2008-03-21

申请人： Toshiharu Furukawa ,  Mark Charles Hakey ,  Steven J. Holmes ,  David Vaclav Horak ,  Charles William Koburger ,  William Robert Tonti

发明人： Toshiharu Furukawa ,  Mark Charles Hakey ,  Steven J. Holmes ,  David Vaclav Horak ,  Charles William Koburger ,  William Robert Tonti

IPC分类号： H01L21/28

CPC分类号： H01L21/76897 ,  H01L21/28052 ,  H01L21/28061 ,  H01L21/28114

摘要： A semiconductor structure. The structure includes (a) a semiconductor layer including a channel region disposed between first and second S/D regions; (b) a gate dielectric region on the channel region; (c) a gate region on the gate dielectric region and electrically insulated from the channel region by the gate dielectric region; (d) a protection umbrella region on the gate region, wherein the protection umbrella region comprises a first dielectric material, and wherein the gate region is completely in a shadow of the protection umbrella region; and (e) a filled contact hole (i) directly above and electrically connected to the second S/D region and (ii) aligned with an edge of the protection umbrella region, wherein the contact hole is physically isolated from the gate region by an inter-level dielectric (ILD) layer which comprises a second dielectric material different from the first dielectric material.

摘要翻译： 半导体结构。 该结构包括（a）包括设置在第一和第二S / D区之间的沟道区的半导体层; （b）沟道区上的栅介质区; （c）栅极电介质区域上的栅极区域，并且通过栅极电介质区域与沟道区域电绝缘; （d）栅极区域上的保护伞区域，其中保护伞区域包括第一介电材料，并且其中栅极区域完全处于保护伞区域的阴影中; 和（e）直接在第二S / D区域上方并电连接到第二S / D区域的填充接触孔（i）和（ii）与保护伞区域的边缘对准，其中接触孔通过一个 层间介电层（ILD）层，其包括不同于第一介电材料的第二电介质材料。

公开(公告)号：US06797641B2

公开(公告)日：2004-09-28

申请号：US10141279

申请日：2002-05-08

申请人： Steven J. Holmes ,  Mark Charles Hakey ,  Toshiharu Furukawa ,  David Vaclav Horak

发明人： Steven J. Holmes ,  Mark Charles Hakey ,  Toshiharu Furukawa ,  David Vaclav Horak

IPC分类号： H01L21302

CPC分类号： H01L21/28194 ,  H01L21/28026 ,  H01L21/28035 ,  H01L21/2807 ,  H01L29/49 ,  H01L29/4975 ,  H01L29/517 ,  H01L29/518 ,  Y10S438/933

摘要： A semi-conductor device includes a silicon substrate. A gate oxide dielectric layer is on the silicon substrate. A gate conductor includes a relatively thin layer of germanium on the dielectric layer. A relatively thick layer of gate conductor material is provided on the layer of germanium. Incorporating germanium at the gate conductor interface with the gate oxide stabilizes the gate oxide by providing a means of drawing charge trapping sites away from the oxide.

摘要翻译： 半导体器件包括硅衬底。 栅极氧化物介电层位于硅衬底上。 栅极导体在电介质层上包括相当薄的锗层。 在锗层上设置较厚的栅导体材料层。 在与栅极氧化物的栅极导体界面处并入锗以通过提供将电荷俘获位置远离氧化物的手段来稳定栅极氧化物。

公开(公告)号：US20080258246A1

公开(公告)日：2008-10-23

申请号：US12166623

申请日：2008-07-02

申请人： Toshiharu Furukawa ,  Mark Charles Hakey ,  Steven John Holmes ,  David Vaclav Horak ,  Charles William Koburger ,  Leah Marie Pfeifer Pastel

发明人： Toshiharu Furukawa ,  Mark Charles Hakey ,  Steven John Holmes ,  David Vaclav Horak ,  Charles William Koburger ,  Leah Marie Pfeifer Pastel

IPC分类号： H01L29/84

CPC分类号： G01P15/0802 ,  B82Y15/00 ,  G01P15/06 ,  G01P15/0891 ,  G01P15/135 ,  H01H1/0094 ,  H01H35/14

摘要： Acceleration and voltage measurement devices and methods of fabricating acceleration and voltage measurement devices. The acceleration and voltage measurement devices including an electrically conductive plate on a top surface of a first insulating layer; a second insulating layer on a top surface of the conductive plate, the top surface of the plate exposed in an opening in the second insulating layer; conductive nanotubes suspended across the opening, and electrically conductive contacts to said nanotubes.

摘要翻译： 加速度和电压测量装置以及制造加速度和电压测量装置的方法。 所述加速和电压测量装置包括在第一绝缘层的顶表面上的导电板; 在所述导电板的顶表面上的第二绝缘层，所述板的顶表面暴露在所述第二绝缘层的开口中; 导电纳米管悬挂在开口上，并与导电接触到所述纳米管。