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102 条记录 (耗时 0.028 秒)

    Semiconductor memory device with predecoder
    61.
    发明授权
    Semiconductor memory device with predecoder 有权
    具有预解码器的半导体存储器件

    公开(公告)号：US6064607A

    公开(公告)日：2000-05-16

    申请号：US177484

    申请日：1998-10-23

    申请人： Takeo Miki ,  Mikio Asakura ,  Satoshi Kawasaki

    发明人： Takeo Miki ,  Mikio Asakura ,  Satoshi Kawasaki

    IPC分类号： G11C8/10 ,  G11C29/00 ,  G11C7/00

    CPC分类号： G11C29/80 ,  G11C8/10

    摘要： Each of first and second program circuits includes a determination node, first to fourth fuses, first to fourth N channel MOS transistors, and first to fourth supply lines. The first to fourth N channel MOS transistors receive first to fourth row address predecode signals, respectively. The first N channel MOS transistor included in the first program circuit and the first N channel MOS transistor included in the second program circuit are arranged adjacent to each other. The first supply line provides a first row address predecode signal to the gate of these two N channel MOS transistors. The same applies for the second to fourth N channel MOS transistors and the second to fourth supply lines. Accordingly, the interconnection capacitance of the row address predecode signal line can be reduced. Also, the size of the transistor driving the row address predecode signal and the transistors in the program circuit can be reduced to allow a smaller layout area for the entire chip.

    摘要翻译： 第一和第二编程电路中的每一个包括确定节点，第一至第四保险丝，第一至第四N沟道MOS晶体管和第一至第四电源线。 第一至第四N沟道MOS晶体管分别接收第一至第四行地址预解码信号。 包括在第一编程电路中的第一N沟道MOS晶体管和包括在第二编程电路中的第一N沟道MOS晶体管彼此相邻布置。 第一电源线为这两个N沟道MOS晶体管的栅极提供第一行地址预解码信号。 同样适用于第二至第四N沟道MOS晶体管和第二至第四供电线。 因此，可以减少行地址预解码信号线的互连电容。 此外，可以减小驱动行地址预解码信号的晶体管的尺寸和程序电路中的晶体管的尺寸，以允许整个芯片的布局面积较小。

    Semiconductor memory device having a multibit test mode
    62.
    发明授权
    Semiconductor memory device having a multibit test mode 有权
    具有多位测试模式的半导体存储器件

    公开(公告)号：US6061808A

    公开(公告)日：2000-05-09

    申请号：US332364

    申请日：1999-06-14

    申请人： Tadaaki Yamauchi ,  Mikio Asakura ,  Takashi Ito

    发明人： Tadaaki Yamauchi ,  Mikio Asakura ,  Takashi Ito

    IPC分类号： G11C11/401 ,  G11C29/00 ,  G11C29/04 ,  G11C29/34 ,  G01R31/28 ,  G06F11/00

    CPC分类号： G11C29/34

    摘要： In a predetermined multibit test mode, a multibit test circuit 114 issues determination result data pairs RDM0 and /RDM0 to RDM3 and /RDM3, each of which corresponds to match/mismatch of logics of data read from memory cells selected by one column select line in corresponding one of memory cell plane blocks. In each memory cell plane block, memory cell columns selected by one single column select line can be replaced as a unit. The unit of memory cell columns containing a defective memory cell is replaced in accordance with determination result data RDM0 and /RDM0 to RDM3 and /RDM3.

    摘要翻译： 在预定的多位测试模式中，多位测试电路114将确定结果数据对RDM0和/ RDM0发送到RDM3和/ RDM3，每个RDM3和/ RDM3对应于从由一列选择线选择的存储器单元读取的数据的逻辑的匹配/不匹配 相应的一个存储单元平面块。 在每个存储单元平面块中，由单个列选择行选择的存储单元列可以被替换为单元。 根据确定结果数据RDM0和/ RDM0至RDM3和/ RDM3来替换包含有缺陷存储单元的存储单元列的单位。

    Semiconductor memory device for simple cache system
    64.
    发明授权
    Semiconductor memory device for simple cache system 失效

    公开(公告)号：US5588130A

    公开(公告)日：1996-12-24

    申请号：US283367

    申请日：1994-08-01

    申请人： Kazuyasu Fujishima ,  Yoshio Matsuda ,  Mikio Asakura

    发明人： Kazuyasu Fujishima ,  Yoshio Matsuda ,  Mikio Asakura

    IPC分类号： G06F12/08 ,  G11C7/10 ,  G06F13/00 ,  G11C15/00

    CPC分类号： G06F12/0893 ,  G11C7/1021

    摘要： A semiconductor memory device comprises a DRAM memory cell array comprising a plurality of dynamic type memory cells arranged in a plurality of rows and columns, and an SRAM memory cell array comprising static type memory cells arranged in a plurality of rows and columns. The DRAM memory cell array is divided into a plurality of blocks each comprising a plurality of columns. The SRAM memory cell array is divided into a plurality of blocks each comprising a plurality of columns, corresponding to the plurality of blocks in the DRAM memory cell array. The SRAM memory cell array is used as a cache memory. At the time of cache hit, data is accessed to the SRAM memory cell array. At the time of cache miss, data is accessed to the DRAM memory cell array. On this occasion, data corresponding to one row in each of the blocks in the DRAM memory cell array is transferred to one row in the corresponding block in the SRAM memory cell array.

    Semiconductor memory device for simple cache system
    66.
    发明授权
    Semiconductor memory device for simple cache system 失效
    半导体存储器件，用于简单缓存系统

    公开(公告)号：US06404691B1

    公开(公告)日：2002-06-11

    申请号：US08472770

    申请日：1995-06-07

    申请人： Kazuyasu Fujishima ,  Yoshio Matsuda ,  Mikio Asakura

    发明人： Kazuyasu Fujishima ,  Yoshio Matsuda ,  Mikio Asakura

    IPC分类号： G11C700

    CPC分类号： G06F12/0893 ,  G11C7/1021

    摘要： A semiconductor memory device comprises a DRAM memory cell array comprising a plurality of dynamic type memory cells arranged in a plurality of rows and columns, and an SRAM memory cell array comprising static type memory cells arranged in a plurality of rows and columns. The DRAM memory cell array is divided into a plurality of blocks each comprising a plurality of columns. The SRAM memory cell array is divided into a plurality of blocks each comprising a plurality of columns, corresponding to the plurality of blocks in the DRAM memory cell array. The SRAM memory cell array is used as a cache memory. At the time of cache hit, data is accessed to the SRAM memory cell array. At the time of cache miss, data is accessed to the DRAM memory cell array. On this occasion, data corresponding to one row in each of the blocks in the DRAM memory cell array is transferred to one row in the corresponding block in the SRAM memory cell array.

    摘要翻译： 一种半导体存储器件包括：DRAM存储单元阵列，包括以多行和多列布置的多个动态型存储单元;以及SRAM存储单元阵列，其包括排列成多行和列的静态型存储单元。 DRAM存储单元阵列被分成多个块，每个块包括多个列。 SRAM存储单元阵列被分成多个块，每个块包括对应于DRAM存储单元阵列中的多个块的多个列。 SRAM存储单元阵列用作高速缓冲存储器。 在缓存命中时，数据被访问到SRAM存储单元阵列。 在缓存未命中时，数据被存取到DRAM存储单元阵列。 在这种情况下，对应于DRAM存储单元阵列中的每个块中的一行的数据被传送到SRAM存储单元阵列中相应块中的一行。

    Semiconductor memory device with IO compression test mode
    67.
    发明授权
    Semiconductor memory device with IO compression test mode 失效
    半导体存储器件具有IO压缩测试模式

    公开(公告)号：US06301169B1

    公开(公告)日：2001-10-09

    申请号：US09658011

    申请日：2000-09-08

    申请人： Shigeru Kikuda ,  Takeshi Hamamoto ,  Mikio Asakura

    发明人： Shigeru Kikuda ,  Takeshi Hamamoto ,  Mikio Asakura

    IPC分类号： G11C700

    CPC分类号： G11C7/1006 ,  G11C29/40

    摘要： In a set of memory cells selected by one column select line, a memory cell of at least 1 bit is connected to an internal data line that is different from the internal data line to which another memory cell in the same set is connected. An internal data line pair is connected to a data terminal. Thus, data having different logic levels can be written into adjacent memory cells even in an IO compression test mode.

    摘要翻译： 在由一列选择线选择的一组存储器单元中，至少1位的存储单元连接到内部数据线，该内部数据线与同一组中的另一个存储单元连接到的内部数据线不同。 内部数据线对连接到数据终端。 因此，即使在IO压缩测试模式下，也可以将具有不同逻辑电平的数据写入相邻存储单元。

    Data output circuit that can drive output data speedily and semiconductor memory device including such a data output circuit
    68.
    发明授权
    Data output circuit that can drive output data speedily and semiconductor memory device including such a data output circuit 失效
    能够快速驱动输出数据的数据输出电路和包括这种数据输出电路的半导体存储器件

    公开(公告)号：US06249462B1

    公开(公告)日：2001-06-19

    申请号：US09557867

    申请日：2000-04-24

    申请人： Koji Tanaka ,  Jun Nakai ,  Yasuhiko Tsukikawa ,  Mikio Asakura

    发明人： Koji Tanaka ,  Jun Nakai ,  Yasuhiko Tsukikawa ,  Mikio Asakura

    IPC分类号： G11C1604

    CPC分类号： G11C7/1069 ,  G11C7/1051 ,  G11C11/4093

    摘要： An output buffer includes a pull up transistor of N type field effect to charge a data output terminal by an external power supply potential Vdd in a high level data output operation, and a pull down transistor of N type field effect to discharge the data output terminal to a ground potential Vss in a low level data output operation. The substrate potential of the pull up NMOS transistor is set to a potential of a level higher than the normal case in a high level data output operation. As a result, the output buffer can speedily charge the data terminal in a high level data output operation.

    摘要翻译： 输出缓冲器包括N型场效应的上拉晶体管，用于在高电平数据输出操作中由外部电源电位Vdd对数据输出端子充电;以及N型场效应的下拉晶体管，以对数据输出端子 到低电平数据输出操作中的地电位Vss。 在高电平数据输出操作中，上拉NMOS晶体管的衬底电位被设置为高于正常情况的电平。 结果，输出缓冲器可以在高电平数据输出操作中对数据终端进行快速充电。