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71 条记录 (耗时 0.049 秒)

    OFDM receiver and metric generator thereof
    61.
    发明申请
    OFDM receiver and metric generator thereof 有权
    OFDM接收机及其度量发生器

    公开(公告)号：US20050002472A1

    公开(公告)日：2005-01-06

    申请号：US10609496

    申请日：2003-07-01

    申请人： Tsung-Lin Lee ,  Rong-Liang Chiou

    发明人： Tsung-Lin Lee ,  Rong-Liang Chiou

    IPC分类号： H04L25/06 ,  H04L27/26 ,  H04L27/38 ,  H04L27/06

    CPC分类号： H04L25/067 ,  H04L1/0054 ,  H04L1/0071 ,  H04L5/0007 ,  H04L5/006 ,  H04L5/0091 ,  H04L27/38

    摘要： A metric generation scheme for use in OFDM receivers. In a preferred embodiment, an OFDM receiver of the invention includes a dynamic quantizer to compress a series of channel-state information values. Also, a bit de-interleaver is provided to de-interleave a series of symbol-based data inverse to interleaving operations at a transmitter end. The de-interleaved symbol-based data is further compressed by another dynamic quantizer to yield a complex signal according to a constellation scheme. Then a metric generator calculates a bit metric of a zero group and a bit metric of a one group for each received bit in which the constellation is divided into the one group and the zero group for each bit location.

    摘要翻译： 用于OFDM接收机的度量生成方案。 在优选实施例中，本发明的OFDM接收机包括用于压缩一系列信道状态信息值的动态量化器。 此外，提供了一个解交织器，用于将一系列基于符号的数据逆交换到发送器端处的交织操作。 解交织的基于符号的数据被另一个动态量化器进一步压缩，以产生根据星座图方案的复信号。 然后，度量发生器为每个接收的比特计算零组的比特量度和一组的比特度量，其中星座被划分成一个组，并且对于每个比特位置分配零组。

    Method of fabricating a SONOS gate structure with dual-thickness oxide
    63.
    发明授权
    Method of fabricating a SONOS gate structure with dual-thickness oxide 有权
    制造具有双重厚度氧化物的SONOS栅极结构的方法

    公开(公告)号：US08653576B2

    公开(公告)日：2014-02-18

    申请号：US12648598

    申请日：2009-12-29

    申请人： Tzyh-Cheang Lee ,  Jiunn-Ren Hwang ,  Tsung-Lin Lee

    发明人： Tzyh-Cheang Lee ,  Jiunn-Ren Hwang ,  Tsung-Lin Lee

    IPC分类号： H01L29/76

    CPC分类号： H01L29/7923 ,  H01L21/28282 ,  H01L29/4234

    摘要： A method of forming a SONOS gate structure. The method includes forming a gate pattern with sidewalls on a substrate, wherein the gate pattern includes a gate dielectric layer patterned on the substrate and a gate electrode patterned on the gate dielectric layer, forming a first oxide layer on the gate pattern and the substrate; etching back the first oxide layer to expose the substrate and the top of the gate electrode, leaving oxide spacers along the sidewalls of the gate pattern respectively; forming a second oxide layer on the substrate and the oxide spacers; and forming trapping dielectric spacers on the second oxide layer adjacent to the sidewalls of the gate pattern respectively.

    摘要翻译： 一种形成SONOS门结构的方法。 该方法包括在衬底上形成具有侧壁的栅极图案，其中栅极图案包括在衬底上图案化的栅极电介质层和在栅极电介质层上图案化的栅电极，在栅极图案和衬底上形成第一氧化物层; 蚀刻第一氧化物层以暴露衬底和栅电极的顶部，分别沿着栅极图案的侧壁留下氧化物间隔物; 在所述衬底和所述氧化物间隔物上形成第二氧化物层; 以及分别在与栅极图案的侧壁相邻的第二氧化物层上形成俘获电介质间隔物。

    Multi-fin device by self-aligned castle fin formation
    67.
    发明授权
    Multi-fin device by self-aligned castle fin formation 有权
    多翅片装置通过自对准城堡鳍形成

    公开(公告)号：US08338305B2

    公开(公告)日：2012-12-25

    申请号：US12907272

    申请日：2010-10-19

    申请人： Hsin-Chih Chen ,  Tsung-Lin Lee ,  Feng Yuan

    发明人： Hsin-Chih Chen ,  Tsung-Lin Lee ,  Feng Yuan

    IPC分类号： H01L21/311

    CPC分类号： H01L29/772 ,  H01L21/3086 ,  H01L29/66795 ,  H01L29/785

    摘要： The present disclosure provides a method includes forming a multi-fin device. The method includes forming a patterned mask layer on a semiconductor substrate. The patterned mask layer includes a first opening having a first width W1 and a second opening having a second width W2 less than the first width. The patterned mask layer defines a multi-fin device region and an inter-device region, wherein the inter-device region is aligned with the first opening; and the multi-fin device region includes at least one intra-device region being aligned with the second opening. The method further includes forming a material layer on the semiconductor substrate and the patterned mask layer, wherein the material layer substantially fills in the second opening; performing a first etching process self-aligned to remove the material layer within the first opening such that the semiconductor substrate within the first opening is exposed; performing a second etching process to etch the semiconductor substrate within the first opening, forming a first trench in the inter-device region; and thereafter performing a third etching process to remove the material layer in the second opening.

    摘要翻译： 本公开提供了一种包括形成多翅片装置的方法。 该方法包括在半导体衬底上形成图案化掩模层。 图案化掩模层包括具有第一宽度W1的第一开口和具有小于第一宽度的第二宽度W2的第二开口。 图案化掩模层限定多鳍器件区域和器件间区域，其中器件间区域与第一开口对准; 并且所述多鳍片器件区域包括与所述第二开口对准的至少一个器件内区域。 该方法还包括在半导体衬底和图案化掩模层上形成材料层，其中材料层基本上填充在第二开口中; 执行自对准的第一蚀刻工艺以去除第一开口内的材料层，使得第一开口内的半导体衬底被暴露; 执行第二蚀刻工艺以在所述第一开口内蚀刻所述半导体衬底，在所述器件间区域中形成第一沟槽; 然后执行第三蚀刻处理以去除第二开口中的材料层。

    STRAINED CHANNEL FIELD EFFECT TRANSISTOR
    68.
    发明申请
    STRAINED CHANNEL FIELD EFFECT TRANSISTOR 有权
    应变通道场效应晶体管

    公开(公告)号：US20120319211A1

    公开(公告)日：2012-12-20

    申请号：US13161649

    申请日：2011-06-16

    申请人： Mark van Dal ,  Gerben Doornbos ,  Georgios Vellianitis ,  Tsung-Lin Lee ,  Feng Yuan

    发明人： Mark van Dal ,  Gerben Doornbos ,  Georgios Vellianitis ,  Tsung-Lin Lee ,  Feng Yuan

    IPC分类号： H01L29/78 ,  H01L21/20

    CPC分类号： H01L29/1054 ,  H01L21/823807 ,  H01L21/823821 ,  H01L27/0924 ,  H01L29/165 ,  H01L29/66795 ,  H01L29/785

    摘要： The present disclosure provides a semiconductor device with a strained SiGe channel and a method for fabricating such a device. In an embodiment, a semiconductor device includes a substrate including at least two isolation features, a fin substrate disposed between and above the at least two isolation features, and an epitaxial layer disposed over exposed portions of the fin substrate. According to one aspect, the epitaxial layer may be disposed over a top surface and sidewalls of the fin substrate. According to another aspect, the fin substrate may be disposed substantially completely above the at least two isolation features.

    摘要翻译： 本公开提供了具有应变SiGe沟道的半导体器件和制造这种器件的方法。 在一个实施例中，半导体器件包括包括至少两个隔离特征的衬底，设置在至少两个隔离特征之间和之上的散热片衬底以及设置在散热片衬底的暴露部分之上的外延层。 根据一个方面，外延层可以设置在翅片衬底的顶表面和侧壁上。 根据另一方面，翅片基板可以基本上完​​全设置在至少两个隔离特征之上。