公开(公告)号：US20120319211A1

公开(公告)日：2012-12-20

申请号：US13161649

申请日：2011-06-16

申请人： Mark van Dal ,  Gerben Doornbos ,  Georgios Vellianitis ,  Tsung-Lin Lee ,  Feng Yuan

发明人： Mark van Dal ,  Gerben Doornbos ,  Georgios Vellianitis ,  Tsung-Lin Lee ,  Feng Yuan

IPC分类号： H01L29/78 ,  H01L21/20

CPC分类号： H01L29/1054 ,  H01L21/823807 ,  H01L21/823821 ,  H01L27/0924 ,  H01L29/165 ,  H01L29/66795 ,  H01L29/785

摘要： The present disclosure provides a semiconductor device with a strained SiGe channel and a method for fabricating such a device. In an embodiment, a semiconductor device includes a substrate including at least two isolation features, a fin substrate disposed between and above the at least two isolation features, and an epitaxial layer disposed over exposed portions of the fin substrate. According to one aspect, the epitaxial layer may be disposed over a top surface and sidewalls of the fin substrate. According to another aspect, the fin substrate may be disposed substantially completely above the at least two isolation features.

摘要翻译： 本公开提供了具有应变SiGe沟道的半导体器件和制造这种器件的方法。 在一个实施例中，半导体器件包括包括至少两个隔离特征的衬底，设置在至少两个隔离特征之间和之上的散热片衬底以及设置在散热片衬底的暴露部分之上的外延层。 根据一个方面，外延层可以设置在翅片衬底的顶表面和侧壁上。 根据另一方面，翅片基板可以基本上完​​全设置在至少两个隔离特征之上。

公开(公告)号：US09761666B2

公开(公告)日：2017-09-12

申请号：US13161649

申请日：2011-06-16

申请人： Mark van Dal ,  Gerben Doornbos ,  Georgios Vellianitis ,  Tsung-Lin Lee ,  Feng Yuan

发明人： Mark van Dal ,  Gerben Doornbos ,  Georgios Vellianitis ,  Tsung-Lin Lee ,  Feng Yuan

IPC分类号： H01L29/78 ,  H01L29/10 ,  H01L29/66 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/165

CPC分类号： H01L29/1054 ,  H01L21/823807 ,  H01L21/823821 ,  H01L27/0924 ,  H01L29/165 ,  H01L29/66795 ,  H01L29/785

摘要： The present disclosure provides a semiconductor device with a strained SiGe channel and a method for fabricating such a device. In an embodiment, a semiconductor device includes a substrate including at least two isolation features, a fin substrate disposed between and above the at least two isolation features, and an epitaxial layer disposed over exposed portions of the fin substrate. According to one aspect, the epitaxial layer may be disposed over a top surface and sidewalls of the fin substrate. According to another aspect, the fin substrate may be disposed substantially completely above the at least two isolation features.

公开(公告)号：US09263342B2

公开(公告)日：2016-02-16

申请号：US13411214

申请日：2012-03-02

申请人： Tsung-Lin Lee ,  Feng Yuan ,  Hung-Li Chiang ,  Chih Chieh Yeh

发明人： Tsung-Lin Lee ,  Feng Yuan ,  Hung-Li Chiang ,  Chih Chieh Yeh

IPC分类号： H01L21/20 ,  H01L21/336 ,  H01L21/8238 ,  H01L29/78 ,  H01L29/66 ,  H01L21/265

CPC分类号： H01L29/66803 ,  H01L21/26513 ,  H01L21/26586 ,  H01L21/30604 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785

摘要： The present disclosure provides devices and methods which provide for strained epitaxial regions. A method of semiconductor fabrication is provided that includes forming a gate structure over a fin of a semiconductor substrate and forming a recess in the fin adjacent the gate structure. A sidewall of the recess is then altered. Exemplary alterations include having an altered profile, treating the sidewall, and forming a layer on the sidewall. An epitaxial region is then grown in the recess. The epitaxial region interfaces the altered sidewall of the recess and is a strained epitaxial region.

摘要翻译： 本公开提供了提供应变外延区域的装置和方法。 提供一种半导体制造方法，其包括在半导体衬底的翅片上形成栅极结构，并在靠近栅极结构的鳍中形成凹陷。 然后改变凹槽的侧壁。 示例性改变包括具有改变的轮廓，处理侧壁以及在侧壁上形成层。 然后在凹槽中生长外延区域。 外延区域与凹陷的改变的侧壁接触并且是应变的外延区域。

公开(公告)号：US20110117679A1

公开(公告)日：2011-05-19

申请号：US12622038

申请日：2009-11-19

申请人： Tsung-Lin Lee ,  Feng Yuan ,  Chih Chieh Yeh

发明人： Tsung-Lin Lee ,  Feng Yuan ,  Chih Chieh Yeh

IPC分类号： H01L21/66 ,  H01L21/336

CPC分类号： H01L29/785 ,  H01L29/41791 ,  H01L29/66795 ,  H01L2029/7858

摘要： A method for fabricating a semiconductor device is disclosed. An exemplary embodiment of the method includes providing a substrate; forming a fin structure over the substrate; forming a gate structure, wherein the gate structure overlies a portion of the fin structure; forming a sacrificial-offset-protection layer over another portion of the fin structure; and thereafter performing an implantation process.

摘要翻译： 公开了一种制造半导体器件的方法。 该方法的示例性实施例包括提供衬底; 在衬底上形成翅片结构; 形成栅极结构，其中所述栅极结构覆盖所述翅片结构的一部分; 在翅片结构的另一部分上形成牺牲偏移保护层; 然后进行植入处理。

公开(公告)号：US09171929B2

公开(公告)日：2015-10-27

申请号：US13487860

申请日：2012-06-04

申请人： Tsung-Lin Lee ,  Chih Chieh Yeh ,  Feng Yuan ,  Cheng-Yi Peng ,  Clement Hsingjen Wann

发明人： Tsung-Lin Lee ,  Chih Chieh Yeh ,  Feng Yuan ,  Cheng-Yi Peng ,  Clement Hsingjen Wann

IPC分类号： H01L29/78 ,  H01L27/092 ,  H01L29/66 ,  H01L29/10 ,  H01L29/165 ,  H01L21/8238 ,  H01L21/02

CPC分类号： H01L29/66636 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/02538 ,  H01L21/0262 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823878 ,  H01L27/0924 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/66651 ,  H01L29/7848

摘要： An exemplary structure for a field effect transistor (FET) comprises a silicon substrate comprising a first surface; a channel portion over the first surface, wherein the channel portion has a second surface at a first height above the first surface, and a length parallel to first surface; and two source/drain (S/D) regions on the first surface and surrounding the channel portion along the length of the channel portion, wherein the two S/D regions comprise SiGe, Ge, Si, SiC, GeSn, SiGeSn, SiSn, or III-V material.

摘要翻译： 用于场效应晶体管（FET）的示例性结构包括：硅衬底，其包括第一表面; 在所述第一表面上的通道部分，其中所述通道部分具有​​在所述第一表面上方的第一高度处的第二表面和平行于第一表面的长度; 以及沿沟道部分的长度围绕沟道部分的两个源极/漏极（S / D）区域，其中两个S / D区域包括SiGe，Ge，Si，SiC，GeSn，SiGeSn，SiSn， 或III-V材料。

公开(公告)号：US20130228862A1

公开(公告)日：2013-09-05

申请号：US13411214

申请日：2012-03-02

申请人： Tsung-Lin Lee ,  Feng Yuan ,  Hung-Li Chiang ,  Chih Chieh Yeh

发明人： Tsung-Lin Lee ,  Feng Yuan ,  Hung-Li Chiang ,  Chih Chieh Yeh

IPC分类号： H01L27/12 ,  H01L21/336 ,  H01L21/20

CPC分类号： H01L29/66803 ,  H01L21/26513 ,  H01L21/26586 ,  H01L21/30604 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785

摘要： The present disclosure provides devices and methods which provide for strained epitaxial regions. A method of semiconductor fabrication is provided that includes forming a gate structure over a fin of a semiconductor substrate and forming a recess in the fin adjacent the gate structure. A sidewall of the recess is then altered. Exemplary alterations include having an altered profile, treating the sidewall, and forming a layer on the sidewall. An epitaxial region is then grown in the recess. The epitaxial region interfaces the altered sidewall of the recess and is a strained epitaxial region.

摘要翻译： 本公开提供了提供应变外延区域的装置和方法。 提供一种半导体制造方法，其包括在半导体衬底的翅片上形成栅极结构，并在与栅极结构相邻的鳍中形成凹陷。 然后改变凹槽的侧壁。 示例性改变包括具有改变的轮廓，处理侧壁以及在侧壁上形成层。 然后在凹槽中生长外延区域。 外延区域与凹陷的改变的侧壁接触并且是应变的外延区域。

公开(公告)号：US08497528B2

公开(公告)日：2013-07-30

申请号：US12775006

申请日：2010-05-06

申请人： Tsung-Lin Lee ,  Chih-Hao Chang ,  Chih-Hsin Ko ,  Feng Yuan ,  Jeff J. Xu

发明人： Tsung-Lin Lee ,  Chih-Hao Chang ,  Chih-Hsin Ko ,  Feng Yuan ,  Jeff J. Xu

IPC分类号： H01L29/66

CPC分类号： H01L29/7848 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/02636 ,  H01L21/30604 ,  H01L21/31 ,  H01L21/31116 ,  H01L21/76 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/0856 ,  H01L29/0873 ,  H01L29/1608 ,  H01L29/165 ,  H01L29/6653 ,  H01L29/66553 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7851

摘要： A structure for a field effect transistor on a substrate that includes a gate stack, an isolation structure and a source/drain (S/D) recess cavity below the top surface of the substrate disposed between the gate stack and the isolation structure. The recess cavity having a lower portion and an upper portion. The lower portion having a first strained layer and a first dielectric film. The first strained layer disposed between the isolation structure and the first dielectric film. A thickness of the first dielectric film less than a thickness of the first strained layer. The upper portion having a second strained layer overlying the first strained layer and first dielectric film.

摘要翻译： 一种用于衬底上的场效应晶体管的结构，其包括栅极堆叠，隔离结构以及位于栅叠层和隔离结构之间的衬底顶表面下方的源极/漏极（S / D）凹槽。 该凹腔具有下部和上部。 下部具有第一应变层和第一介电膜。 第一应变层设置在隔离结构和第一介电膜之间。 第一电介质膜的厚度小于第一应变层的厚度。 上部具有覆盖在第一应变层和第一介电膜上的第二应变层。

公开(公告)号：US08373238B2

公开(公告)日：2013-02-12

申请号：US12843595

申请日：2010-07-26

申请人： Tsung-Lin Lee ,  Chih Chieh Yeh ,  Chang-Yun Chang ,  Feng Yuan

发明人： Tsung-Lin Lee ,  Chih Chieh Yeh ,  Chang-Yun Chang ,  Feng Yuan

IPC分类号： H01L27/088

CPC分类号： H01L29/66666 ,  H01L21/76 ,  H01L21/823431 ,  H01L27/0886 ,  H01L29/66795 ,  H01L29/785

摘要： An integrated circuit structure includes a semiconductor substrate, and a FinFET over the semiconductor substrate. The FinFET includes a semiconductor fin; a gate dielectric on a top surface and sidewalls of the semiconductor fin; a gate electrode on the gate dielectric; and a source/drain region at an end of the semiconductor fin. A first pair of shallow trench isolation (STI) regions includes portions directly underlying portions of the source/drain regions, wherein the first pair of STI regions is separated by, and adjoining a semiconductor strip. The first pair of STI regions further has first top surfaces. A second pair of STI regions comprises portions directly underlying the gate electrode, wherein the second pair of STI regions is separated from each other by, and adjoining, the semiconductor strip. The second pair of STI regions has second top surfaces higher than the first top surfaces.

摘要翻译： 集成电路结构包括半导体衬底和半导体衬底上的FinFET。 FinFET包括半导体鳍片; 顶表面上的栅极电介质和半导体鳍片的侧壁; 栅电极上的栅电极; 以及在半导体鳍片的端部处的源极/漏极区域。 第一对浅沟槽隔离（STI）区域包括直接在源极/漏极区域的下方部分的部分，其中第一对STI区域被分隔开并邻接半导体条带。 第一对STI区域还具有第一顶面。 第二对STI区域包括直接位于栅极电极下方的部分，其中第二对STI区域彼此分离并邻接半导体条带。 第二对STI区域具有高于第一顶表面的第二顶表面。

公开(公告)号：US20110121406A1

公开(公告)日：2011-05-26

申请号：US12871655

申请日：2010-08-30

申请人： Tsung-Lin Lee ,  Chih Cheih Yeh ,  Chang-Yun Chang ,  Feng Yuan

发明人： Tsung-Lin Lee ,  Chih Cheih Yeh ,  Chang-Yun Chang ,  Feng Yuan

IPC分类号： H01L27/088 ,  H01L21/28

CPC分类号： H01L21/823431 ,  H01L21/266 ,  H01L21/76224 ,  H01L21/823437 ,  H01L21/823481 ,  H01L27/0886 ,  H01L27/1104 ,  H01L27/1116 ,  H01L29/0649 ,  H01L29/41791 ,  H01L29/66795 ,  H01L29/785

摘要： An integrated circuit structure includes a semiconductor substrate including a first portion in a first device region, and a second portion in a second device region. A first semiconductor fin is over the semiconductor substrate and has a first fin height. A second semiconductor fin is over the semiconductor substrate and has a second fin height. The first fin height is greater than the second fin height.

摘要翻译： 集成电路结构包括包括第一器件区域中的第一部分和第二器件区域中的第二部分的半导体衬底。 第一半导体鳍片在半导体衬底之上并且具有第一鳍片高度。 第二半导体鳍片在半导体衬底之上并且具有第二鳍片高度。 第一鳍高度大于第二翅片高度。

公开(公告)号：US09953885B2

公开(公告)日：2018-04-24

申请号：US12843693

申请日：2010-07-26

申请人： Feng Yuan ,  Tsung-Lin Lee ,  Hung-Ming Chen ,  Chang-Yun Chang

发明人： Feng Yuan ,  Tsung-Lin Lee ,  Hung-Ming Chen ,  Chang-Yun Chang

IPC分类号： H01L21/76 ,  H01L21/84 ,  H01L21/762 ,  H01L21/8234 ,  H01L29/66

CPC分类号： H01L21/845 ,  H01L21/76224 ,  H01L21/823431 ,  H01L29/66795

摘要： A method of forming an integrated circuit structure includes providing a semiconductor substrate including a top surface; forming a first insulation region and a second insulation region in the semiconductor substrate; and recessing the first insulation region and the second insulation region. Top surfaces of remaining portions of the first insulation region and the second insulation region are flat surfaces or divot surfaces. A portion of the semiconductor substrate between and adjoining removed portions of the first insulation region and the second insulation region forms a fin.