公开(公告)号：US20200212290A1

公开(公告)日：2020-07-02

申请号：US16255754

申请日：2019-01-23

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hui-Lin Wang ,  Tai-Cheng Hou ,  Wei-Xin Gao ,  Fu-Yu Tsai ,  Chin-Yang Hsieh ,  Chen-Yi Weng ,  Jing-Yin Jhang ,  Bin-Siang Tsai ,  Kun-Ju Li ,  Chih-Yueh Li ,  Chia-Lin Lu ,  Chun-Lung Chen ,  Kun-Yuan Liao ,  Yu-Tsung Lai ,  Wei-Hao Huang

IPC: H01L41/47 ,  H01L21/762 ,  H01L43/02 ,  H01L21/768

Abstract: A method for fabricating semiconductor device includes the steps of: forming a first magnetic tunneling junction (MTJ) on a substrate; forming a first ultra low-k (ULK) dielectric layer on the first MTJ; performing a first etching process to remove part of the first ULK dielectric layer and forming a damaged layer on the first ULK dielectric layer; and forming a second ULK dielectric layer on the damaged layer.

公开(公告)号：US20200176510A1

公开(公告)日：2020-06-04

申请号：US16214127

申请日：2018-12-09

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hui-Lin Wang ,  Chia-Chang Hsu ,  Chen-Yi Weng ,  Hung-Chan Lin ,  Jing-Yin Jhang ,  Yu-Ping Wang

IPC: H01L27/22 ,  G11C11/16 ,  H01L23/48 ,  H01L23/485 ,  H01L23/544 ,  H01L21/321 ,  H01L21/762 ,  H01L43/12

Abstract: The disclosure provides a semiconductor memory device including a substrate having a memory cell region and an alignment mark region; a dielectric layer covering the memory cell region and the alignment mark region; conductive vias in the dielectric layer within the memory cell region; an alignment mark trench in the dielectric layer within the alignment mark region; and storage structures disposed on the conductive vias, respectively. Each of the storage structures includes a bottom electrode defined from a bottom electrode metal layer, a magnetic tunnel junction (MTJ) structure defined from an MTJ layer, and a top electrode. A residual metal stack is left in the alignment mark trench. The residual metal stack includes a portion of the bottom electrode metal layer and a portion of the MTJ layer.

公开(公告)号：US09666715B2

公开(公告)日：2017-05-30

申请号：US14599556

申请日：2015-01-19

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chung-Fu Chang ,  Chun-Hsien Lin ,  Chen-Yi Weng

IPC: H01L29/78 ,  H01L29/66

CPC classification number: H01L29/7848 ,  H01L29/66795 ,  H01L29/785

Abstract: A field effect transistor with epitaxial structures includes a fin-shaped structure and a metal gate across the fin-shaped structure. The metal gate includes a pair of recess regions disposed on two sides of the bottom of the metal gate.

公开(公告)号：US09530871B1

公开(公告)日：2016-12-27

申请号：US15225836

申请日：2016-08-02

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ming-Yueh Tsai ,  Jia-Feng Fang ,  Yi-Wei Chen ,  Jing-Yin Jhang ,  Rung-Yuan Lee ,  Chen-Yi Weng ,  Wei-Jen Wu

IPC: H01L21/8232 ,  H01L29/66 ,  H01L21/02 ,  H01L21/324

CPC classification number: H01L29/66795 ,  H01L21/02126 ,  H01L21/0214 ,  H01L21/02164 ,  H01L21/324 ,  H01L21/76829 ,  H01L21/76832 ,  H01L21/76834 ,  H01L29/0847 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/165 ,  H01L29/7848 ,  H01L29/7851

Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having a fin-shaped structure thereon; forming an epitaxial layer on the fin-shaped structure; forming a first contact etch stop layer (CESL) on the epitaxial layer; forming a source/drain region in the epitaxial layer; and forming a second CESL on the first CESL.

Abstract translation: 公开了半导体器件的制造方法。 该方法包括以下步骤：提供其上具有鳍状结构的基板; 在鳍状结构上形成外延层; 在外延层上形成第一接触蚀刻停止层（CESL）; 在外延层中形成源/漏区; 并在第一个CESL上形成第二个CESL。

公开(公告)号：US09443757B1

公开(公告)日：2016-09-13

申请号：US14940120

申请日：2015-11-12

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ming-Yueh Tsai ,  Jia-Feng Fang ,  Yi-Wei Chen ,  Jing-Yin Jhang ,  Rung-Yuan Lee ,  Chen-Yi Weng ,  Wei-Jen Wu

IPC: H01L29/78 ,  H01L21/768 ,  H01L29/161 ,  H01L29/16 ,  H01L29/165 ,  H01L29/08 ,  H01L23/535 ,  H01L29/66

CPC classification number: H01L29/66795 ,  H01L21/02126 ,  H01L21/0214 ,  H01L21/02164 ,  H01L21/324 ,  H01L21/76829 ,  H01L21/76832 ,  H01L21/76834 ,  H01L29/0847 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/165 ,  H01L29/7848 ,  H01L29/7851

Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having a fin-shaped structure thereon; forming an epitaxial layer on the fin-shaped structure; forming a first contact etch stop layer (CESL) on the epitaxial layer; forming a source/drain region in the epitaxial layer; and forming a second CESL on the first CESL.

Abstract translation: 公开了半导体器件的制造方法。 该方法包括以下步骤：提供其上具有鳍状结构的基板; 在鳍状结构上形成外延层; 在外延层上形成第一接触蚀刻停止层（CESL）; 在外延层中形成源/漏区; 并在第一个CESL上形成第二个CESL。

公开(公告)号：US20240334836A1

公开(公告)日：2024-10-03

申请号：US18142036

申请日：2023-05-02

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hui-Lin Wang ,  Ching-Hua Hsu ,  Che-Wei Chang ,  Chen-Yi Weng

IPC: H10N50/01 ,  G11C11/16 ,  H10B61/00 ,  H10N50/10 ,  H10N50/80

CPC classification number: H10N50/01 ,  G11C11/161 ,  H10B61/00 ,  H10N50/10 ,  H10N50/80

Abstract: A method for fabricating a semiconductor device includes the steps of providing a substrate comprising a magnetic random access memory (MRAM) region and a logic region, forming a first magnetic tunneling junction (MTJ) on the MRAM region, forming a first inter-metal dielectric (IMD) layer around the first MTJ, and then forming a first metal interconnection extending from the MRAM region to the logic region on the first MTJ. Preferably, the first metal interconnection on the MRAM region and the first metal interconnection on the logic region have different heights.

公开(公告)号：US12102014B2

公开(公告)日：2024-09-24

申请号：US18376437

申请日：2023-10-03

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hui-Lin Wang ,  Chia-Chang Hsu ,  Chen-Yi Weng ,  Chin-Yang Hsieh ,  Jing-Yin Jhang

IPC: H10B61/00 ,  G11C11/16 ,  H01F10/32 ,  H01F41/34 ,  H10N50/01 ,  H10N50/80 ,  H10N50/85

CPC classification number: H10N50/80 ,  G11C11/161 ,  H01F10/3254 ,  H01F41/34 ,  H10B61/00 ,  H10N50/01 ,  H10N50/85

Abstract: A semiconductor device includes a substrate comprising a MTJ region and a logic region, a magnetic tunneling junction (MTJ) on the MTJ region, and a contact plug on the logic region. Preferably, the MTJ includes a bottom electrode layer having a gradient concentration, a free layer on the bottom electrode layer, and a top electrode layer on the free layer.

公开(公告)号：US20240306514A1

公开(公告)日：2024-09-12

申请号：US18126486

申请日：2023-03-27

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hui-Lin Wang ,  Che-Wei Chang ,  Ching-Hua Hsu ,  Chen-Yi Weng ,  Po-Kai Hsu

IPC: H10N50/10 ,  H01L23/522 ,  H01L23/528 ,  H10B61/00 ,  H10N50/80

CPC classification number: H10N50/10 ,  H01L23/5226 ,  H01L23/5283 ,  H10B61/00 ,  H10N50/80

Abstract: A magnetic random access memory structure includes a first dielectric layer; a bottom electrode layer disposed on the first dielectric layer; a spin orbit coupling layer disposed on the bottom electrode layer; a magnetic tunneling junction (MTJ) element disposed on the spin orbit coupling layer; a top electrode layer disposed on the MTJ element; a protective layer surrounding the MTJ element and the top electrode layer, and the protective layer masking the spin orbit coupling layer; and a spacer layer surrounding the protective layer.

公开(公告)号：US12029139B2

公开(公告)日：2024-07-02

申请号：US18202275

申请日：2023-05-25

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hui-Lin Wang ,  Yu-Ping Wang ,  Chen-Yi Weng ,  Chin-Yang Hsieh ,  Si-Han Tsai ,  Che-Wei Chang ,  Jing-Yin Jhang

IPC: H10N50/80 ,  H10B61/00 ,  H10N50/01 ,  H10N50/85

CPC classification number: H10N50/80 ,  H10B61/00 ,  H10N50/01 ,  H10N50/85

Abstract: A semiconductor device includes: a substrate comprising a magnetic tunneling junction (MTJ) region and a logic region; a first MTJ on the MTJ region; a first metal interconnection on the logic region; and a cap layer extending from a sidewall of the first MTJ to a sidewall of the first metal interconnection. Preferably, the cap layer on the MTJ region and the cap layer on the logic region comprise different thicknesses.

公开(公告)号：US11957064B2

公开(公告)日：2024-04-09

申请号：US17967904

申请日：2022-10-18

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hui-Lin Wang ,  Chen-Yi Weng ,  Yi-Wei Tseng ,  Chin-Yang Hsieh ,  Jing-Yin Jhang ,  Yi-Hui Lee ,  Ying-Cheng Liu ,  Yi-An Shih ,  I-Ming Tseng ,  Yu-Ping Wang

IPC: H10N50/80 ,  G11C5/06 ,  G11C11/16 ,  H01L29/82 ,  H10N50/01 ,  H10N50/10 ,  H10B61/00

CPC classification number: H10N50/80 ,  G11C5/06 ,  G11C11/16 ,  G11C11/161 ,  H01L29/82 ,  H10N50/01 ,  H10N50/10 ,  G11C2211/5615 ,  H10B61/00

Abstract: A semiconductor device includes a magnetic tunneling junction (MTJ) on a substrate, a spacer adjacent to the MTJ, a liner adjacent to the spacer, and a first metal interconnection on the MTJ. Preferably, the first metal interconnection includes protrusions adjacent to two sides of the MTJ and a bottom surface of the protrusions contact the liner directly.