公开(公告)号：US20060270066A1

公开(公告)日：2006-11-30

申请号：US11405514

申请日：2006-04-18

申请人： Ryota Imahayashi ,  Shinobu Furukawa ,  Atsuo Isobe ,  Yasuyuki Arai ,  Shunpei Yamazaki

发明人： Ryota Imahayashi ,  Shinobu Furukawa ,  Atsuo Isobe ,  Yasuyuki Arai ,  Shunpei Yamazaki

IPC分类号： H01L21/00

CPC分类号： H01L51/0512 ,  H01L21/02175 ,  H01L21/02244 ,  H01L21/02247 ,  H01L21/02252 ,  H01L21/31683 ,  H01L51/0002 ,  H01L51/0055 ,  H01L51/0525 ,  H01L51/0541 ,  H01L51/0545 ,  H01L51/0566

摘要： It is an object to form a high quality gate insulating film which is dense and has a strong insulation resistance property, and to propose a high reliable organic transistor in which a tunnel leakage current is little. One mode of the organic transistor of the present invention has a step of forming the gate insulating film by forming the conductive layer which becomes the gate electrode activating oxygen (or gas including oxygen) or nitrogen (or gas including nitrogen) or the like using dense plasma in which density of electron is 1011 cm−3 or more, and electron temperature is a range of 0.2 eV to 2.0 eV with plasma activation, and reacting directly with a portion of the conductive layer which becomes the gate electrode to be insulated.

摘要翻译： 本发明的目的是形成致密且具有很强绝缘电阻特性的高质量栅极绝缘膜，并且提出了隧道泄漏电流很小的高可靠性有机晶体管。 本发明的有机晶体管的一种模式具有如下步骤：通过使用密集的方法形成作为活化氧（或含氧气体）或氮（或含氮气体）的栅极的导电层形成栅极绝缘膜 等离子体，其中电子密度为10〜30cm -3以上，等离子体激活时电子温度为0.2eV〜2.0eV，直接与 作为要被绝缘的栅电极的导电层的一部分。

公开(公告)号：US07078768B2

公开(公告)日：2006-07-18

申请号：US10815701

申请日：2004-04-02

申请人： Shunpei Yamazaki ,  Etsuko Fujimoto ,  Atsuo Isobe ,  Toru Takayama ,  Kunihiko Fukuchi

发明人： Shunpei Yamazaki ,  Etsuko Fujimoto ,  Atsuo Isobe ,  Toru Takayama ,  Kunihiko Fukuchi

IPC分类号： H01L27/12

CPC分类号： H01L29/4908 ,  H01L27/124 ,  H01L27/1248 ,  H01L27/1255 ,  H01L27/1277 ,  H01L29/42384

摘要： A semiconductor device and a process for production thereof, said semiconductor device having a new electrode structure which has a low resistivity and withstands heat treatment at 400° C. and above. Heat treatment at a high temperature (400–700° C.) is possible because the wiring is made of Ta film or Ta-based film having high heat resistance. This heat treatment permits the gettering of metal element in crystalline silicon film. Since this heat treatment is lower than the temperature which the gate wiring (0.1–5 μm wide) withstands and the gate wiring is protected with a protective film, the gate wiring retains its low resistance.

公开(公告)号：US20060071210A1

公开(公告)日：2006-04-06

申请号：US11148289

申请日：2005-06-09

申请人： Shunpei Yamazaki ,  Atsuo Isobe ,  Tetsuji Yamaguchi ,  Hiromichi Godo

发明人： Shunpei Yamazaki ,  Atsuo Isobe ,  Tetsuji Yamaguchi ,  Hiromichi Godo

IPC分类号： H01L31/0376

CPC分类号： H01L27/127 ,  H01L27/1214 ,  H01L27/1285 ,  H01L27/1288 ,  H01L27/13 ,  H01L29/458 ,  H01L29/4908 ,  H01L29/78621 ,  H01L29/78624

摘要： It is an object of the present invention to manufacture a thin film transistor having a required property without complicating steps and devices. It is another object of the present invention to provide a technique for manufacturing a semiconductor device having high reliability and better electrical characteristics with a higher yield at lower cost. In the present invention, a lightly doped impurity region is formed in a source region side or a drain region side of a semiconductor layer covered with a gate electrode layer in a thin film transistor. The semiconductor layer is doped diagonally to the surface thereof using the gate electrode layer as a mask to form the lightly doped impurity region. Therefore, the properties of the thin film transistor can be minutely controlled.

摘要翻译： 本发明的目的是制造具有所需性能的薄膜晶体管，而不会使步骤和装置复杂化。 本发明的另一个目的是提供一种以更低的成本制造具有高可靠性和更好的电气特性并以较高产量获得的半导体器件的技术。 在本发明中，在薄膜晶体管中由栅极电极层覆盖的半导体层的源区域侧或漏极区侧形成有轻掺杂杂质区。 使用栅极电极层作为掩模将半导体层以其对面的方式对角地掺杂以形成轻掺杂杂质区域。 因此，可以精细地控制薄膜晶体管的性质。

公开(公告)号：US20050274952A1

公开(公告)日：2005-12-15

申请号：US11148426

申请日：2005-06-09

申请人： Shunpei Yamazaki ,  Atsuo Isobe ,  Tetsuji Yamaguchi ,  Hiromichi Godo

发明人： Shunpei Yamazaki ,  Atsuo Isobe ,  Tetsuji Yamaguchi ,  Hiromichi Godo

IPC分类号： H01L21/265 ,  H01L21/336 ,  H01L21/77 ,  H01L29/10 ,  H01L29/786

CPC分类号： H01L27/1214 ,  H01L21/26586 ,  H01L27/127 ,  H01L27/1274 ,  H01L29/66757 ,  H01L29/78624

摘要： In the invention, a low concentration impurity region is formed between a channel formation region and a source region or a drain region in a semiconductor layer and covered with a gate electrode layer in a thin film transistor The semiconductor layer is doped obliquely to the surface thereof using the gate electrode layer as a mask to form the low concentration impurity region. The semiconductor layer is formed to have an impurity region including an impurity element for imparting one conductivity which is different from conductivity of the thin film transistor, thereby being able to minutely control the properties of the thin film transistor.

摘要翻译： 在本发明中，在半导体层中的沟道形成区域和源极区域或漏极区域之间形成低浓度杂质区域，并且在薄膜晶体管中被栅极电极层覆盖。半导体层倾斜地掺杂在其表面上 使用栅极电极层作为掩模形成低浓度杂质区域。 半导体层形成为具有包含用于赋予与薄膜晶体管的导电性不同的一种导电性的杂质元素的杂质区域，从而能够精细地控制薄膜晶体管的性质。

公开(公告)号：US06841797B2

公开(公告)日：2005-01-11

申请号：US10338043

申请日：2003-01-08

申请人： Atsuo Isobe ,  Shunpei Yamazaki ,  Koji Dairiki ,  Hiroshi Shibata ,  Chiho Kokubo ,  Tatsuya Arao ,  Masahiko Hayakawa ,  Hidekazu Miyairi ,  Akihisa Shimomura ,  Koichiro Tanaka ,  Mai Akiba

发明人： Atsuo Isobe ,  Shunpei Yamazaki ,  Koji Dairiki ,  Hiroshi Shibata ,  Chiho Kokubo ,  Tatsuya Arao ,  Masahiko Hayakawa ,  Hidekazu Miyairi ,  Akihisa Shimomura ,  Koichiro Tanaka ,  Mai Akiba

IPC分类号： H01L21/20 ,  H01L21/336 ,  H01L21/77 ,  H01L21/84 ,  H01L27/12 ,  H01L29/786 ,  H01L31/36

CPC分类号： H01L27/1222 ,  B23K26/0738 ,  H01L21/02354 ,  H01L21/02356 ,  H01L21/02675 ,  H01L21/02683 ,  H01L21/02686 ,  H01L21/02691 ,  H01L21/2026 ,  H01L21/32139 ,  H01L21/84 ,  H01L27/1214 ,  H01L27/1218 ,  H01L27/124 ,  H01L27/1255 ,  H01L27/1274 ,  H01L27/1281 ,  H01L27/1296 ,  H01L29/66757 ,  H01L29/78603 ,  H01L29/78675 ,  H01L29/78696 ,  Y10S118/90 ,  Y10T117/10 ,  Y10T117/1004 ,  Y10T117/1008

摘要： A semiconductor device production system using a laser crystallization method is provided which can avoid forming grain boundaries in a channel formation region of a TFT, thereby preventing grain boundaries from lowering the mobility of the TFT greatly, from lowering ON current, and from increasing OFF current. Rectangular or stripe pattern depression and projection portions are formed on an insulating film. A semiconductor film is formed on the insulating film. The semiconductor film is irradiated with continuous wave laser light by running the laser light along the stripe pattern depression and projection portions of the insulating film or along the major or minor axis direction of the rectangle. Although continuous wave laser light is most preferred among laser light, it is also possible to use pulse oscillation laser light in irradiating the semiconductor film.

摘要翻译： 提供了一种使用激光晶化方法的半导体器件制造系统，其可以避免在TFT的沟道形成区域中形成晶界，从而防止晶界大大降低TFT的迁移率，降低导通电流，并且提高截止电流 。 在绝缘膜上形成矩形或条纹图案凹陷和突出部分。 在绝缘膜上形成半导体膜。 通过沿着条形图案凹陷和绝缘膜的突出部分沿着矩形的长轴或短轴方向运行激光来对连续波激光照射半导体膜。 尽管在激光中最优选连续波激光，但也可以在照射半导体膜时使用脉冲振荡激光。

公开(公告)号：US06399960B1

公开(公告)日：2002-06-04

申请号：US09353370

申请日：1999-07-14

申请人： Shunpei Yamazaki ,  Etsuko Fujimoto ,  Atsuo Isobe ,  Toru Takayama ,  Kunihiko Fukuchi

发明人： Shunpei Yamazaki ,  Etsuko Fujimoto ,  Atsuo Isobe ,  Toru Takayama ,  Kunihiko Fukuchi

IPC分类号： H01L3300

CPC分类号： H01L27/1237 ,  G02F1/13454 ,  H01L27/1248 ,  H01L29/458 ,  H01L29/4908 ,  H01L29/78645

摘要： The invention is to provide a high-productivity method for fabricating a TFT device having different LDD structures on one and the same substrate, and the TFT device. Specifically, the invention provides a novel TFT structure, and a high-productivity method for fabricating it. A Ta film or a Ta-based film having good heat resistance is used for forming interconnections, and the interconnections are covered with a protective film. The interconnections can be subjected to heat treatment at high temperatures (400 to 700° C.), and, in addition, the protective film serves as an etching stopper. In the peripheral driving circuit portion in the device, TFTs having an LDD structure are disposed in a self-aligned process in which is used side walls 126 and 127; while in the pixel matrix portion therein, TFTs having an LDD structure are disposed in a non-self-aligned process in which is used an insulator 125.

摘要翻译： 本发明提供一种用于制造在同一基板上具有不同LDD结构的TFT器件和TFT器件的高生产率方法。 具体地说，本发明提供了一种新颖的TFT结构，以及高生产率的制造方法。 使用具有良好耐热性的Ta膜或Ta基膜形成互连，并且互连用保护膜覆盖。 互连可以在高温（400〜700℃）下进行热处理，另外，保护膜用作蚀刻停止体。 在器件的外围驱动电路部分中，具有LDD结构的TFT以自对准工艺设置，其中使用侧壁126和127; 而在其中的像素矩阵部分中，具有LDD结构的TFT被设置在非自对准工艺中，其中使用绝缘体125。

公开(公告)号：US08847233B2

公开(公告)日：2014-09-30

申请号：US13463092

申请日：2012-05-03

申请人： Atsuo Isobe ,  Toshinari Sasaki ,  Junichi Koezuka ,  Shunpei Yamazaki

发明人： Atsuo Isobe ,  Toshinari Sasaki ,  Junichi Koezuka ,  Shunpei Yamazaki

IPC分类号： H01L29/04 ,  H01L29/10 ,  H01L31/036 ,  H01L31/0376 ,  H01L31/20 ,  H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119 ,  H01L27/01 ,  H01L27/12 ,  H01L31/0392 ,  H01L27/108 ,  H01L21/84 ,  H01L49/02 ,  H01L21/425 ,  H01L29/66 ,  H01L29/786 ,  H01L27/115

CPC分类号： H01L29/4238 ,  H01L21/02565 ,  H01L21/265 ,  H01L21/425 ,  H01L21/84 ,  H01L27/1085 ,  H01L27/10876 ,  H01L27/1156 ,  H01L27/1203 ,  H01L27/1225 ,  H01L28/40 ,  H01L29/045 ,  H01L29/0847 ,  H01L29/66477 ,  H01L29/66742 ,  H01L29/66969 ,  H01L29/78603 ,  H01L29/7869 ,  H01L29/78693

摘要： It is an object to provide a semiconductor device in which a short-channel effect is suppressed and miniaturization is achieved, and a manufacturing method thereof. A trench is formed in an insulating layer and impurities are added to an oxide semiconductor film in contact with an upper end corner portion of the trench, whereby a source region and a drain region are formed. With the above structure, miniaturization can be achieved. Further, with the trench, a short-channel effect can be suppressed setting the depth of the trench as appropriate even when a distance between a source electrode layer and a drain electrode layer is shortened.

摘要翻译： 本发明的目的是提供一种抑制短路效应并实现小型化的半导体器件及其制造方法。 在绝缘层中形成沟槽，并且将杂质添加到与沟槽的上端角部接触的氧化物半导体膜，由此形成源极区域和漏极区域。 利用上述结构，可以实现小型化。 此外，利用沟槽，即使当源电极层和漏电极层之间的距离缩短时，也可以适当地抑制沟槽的深度适当地设定短沟道效应。

公开(公告)号：US08822989B2

公开(公告)日：2014-09-02

申请号：US13613178

申请日：2012-09-13

申请人： Shunpei Yamazaki ,  Atsuo Isobe ,  Toshinari Sasaki

发明人： Shunpei Yamazaki ,  Atsuo Isobe ,  Toshinari Sasaki

IPC分类号： H01L29/10 ,  H01L29/786 ,  H01L27/12

CPC分类号： H01L29/7869 ,  H01L27/12 ,  H01L27/1225 ,  H01L29/10 ,  H01L29/41733 ,  H01L29/41775

摘要： Provided is a semiconductor device including a transistor with large on-state current even when it is miniaturized. The transistor includes a pair of first conductive films over an insulating surface; a semiconductor film over the pair of first conductive films; a pair of second conductive films, with one of the pair of second conductive films and the other of the pair of second conductive films being connected to one of the pair of first conductive films and the other of the pair of first conductive films, respectively; an insulating film over the semiconductor film; and a third conductive film provided in a position overlapping with the semiconductor film over the insulating film. Further, over the semiconductor film, the third conductive film is interposed between the pair of second conductive films and away from the pair of second conductive films.

摘要翻译： 提供了即使在小型化时也具有大导通状态的晶体管的半导体装置。 晶体管包括在绝缘表面上的一对第一导电膜; 在一对第一导电膜上的半导体膜; 一对第二导电膜，其中一对第二导电膜中的一个和一对第二导电膜中的另一个分别连接到一对第一导电膜中的一个和一对第一导电膜中的另一个; 半导体膜上的绝缘膜; 以及设置在与绝缘膜上的半导体膜重叠的位置的第三导电膜。 此外，在半导体膜之上，第三导电膜插入在一对第二导电膜之间并远离一对第二导电膜。

公开(公告)号：US07795734B2

公开(公告)日：2010-09-14

申请号：US11636598

申请日：2006-12-11

申请人： Atsuo Isobe ,  Shunpei Yamazaki ,  Chiho Kokubo ,  Koichiro Tanaka ,  Akihisa Shimomura ,  Tatsuya Arao ,  Hidekazu Miyairi

发明人： Atsuo Isobe ,  Shunpei Yamazaki ,  Chiho Kokubo ,  Koichiro Tanaka ,  Akihisa Shimomura ,  Tatsuya Arao ,  Hidekazu Miyairi

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC分类号： H01L29/78696 ,  H01L27/12 ,  H01L27/1281 ,  H01L27/3244 ,  H01L29/04 ,  H01L29/66757 ,  H01L29/78621 ,  H01L29/78675

摘要： To provide a semiconductor device composed of a semiconductor element or a group of semiconductor elements, in which a crystalline semiconductor film having as few grain boundaries as possible in a channel formation region is formed on an insulating surface, which can operate at high speed, which have high current drive performance, and which are less fluctuated between elements. The method of the present invention includes: forming an insulating film with an opening on a substrate having an insulating surface; forming on the insulating film and over the opening an amorphous semiconductor film or a polycrystalline semiconductor film that has randomly-formed grain boundaries; forming a crystalline semiconductor film by melting the semiconductor film, pouring the melted semiconductor into the opening of the insulating film, and crystallizing or re-crystallizing the semiconductor film; and removing the crystalline semiconductor film except a portion of the crystalline semiconductor film that is in the opening to form a gate insulating film, which is in contact with the top face of the crystalline semiconductor film, and a gate electrode.

摘要翻译： 为了提供一种由半导体元件或一组半导体元件组成的半导体器件，其中在绝缘表面上形成可在沟道形成区域中具有尽可能少的晶界的结晶半导体膜，其可以高速操作，其中 具有高电流驱动性能，并且元件之间波动较小。 本发明的方法包括：在具有绝缘表面的基板上形成具有开口的绝缘膜; 在绝缘膜上和开口上形成非晶半导体膜或随机形成晶界的多晶半导体膜; 通过熔化半导体膜形成晶体半导体膜，将熔融的半导体注入到绝缘膜的开口中，并使半导体膜结晶或再结晶; 以及去除除了开口中的结晶半导体膜的部分之外的晶体半导体膜以形成与晶体半导体膜的顶面接触的栅极绝缘膜和栅电极。

公开(公告)号：US07749818B2

公开(公告)日：2010-07-06

申请号：US10352233

申请日：2003-01-28

申请人： Atsuo Isobe ,  Shunpei Yamazaki ,  Chiho Kokubo ,  Koichiro Tanaka ,  Akihisa Shimomura ,  Tatsuya Arao ,  Hidekazu Miyairi ,  Mai Akiba

发明人： Atsuo Isobe ,  Shunpei Yamazaki ,  Chiho Kokubo ,  Koichiro Tanaka ,  Akihisa Shimomura ,  Tatsuya Arao ,  Hidekazu Miyairi ,  Mai Akiba

IPC分类号： H01L21/00 ,  H01L21/84

CPC分类号： H01L29/78696 ,  H01L27/12 ,  H01L27/1281 ,  H01L27/148 ,  H01L29/04 ,  H01L29/66757 ,  H01L29/785 ,  H01L29/78621 ,  H01L29/78675

摘要： An objective is to provide a method of manufacturing a semiconductor device, and a semiconductor device manufactured by using the manufacturing method, in which a laser crystallization method is used that is capable of preventing the formation of grain boundaries in TFT channel formation regions, and is capable of preventing conspicuous drops in TFT mobility, reduction in the ON current, and increases in the OFF current, all due to grain boundaries. Stripe shape or rectangular shape unevenness or opening is formed. Continuous wave laser light is then irradiated to a semiconductor film formed on an insulating film. Note that although it is most preferable to use continuous wave laser light at this point, pulse wave oscillation laser light may also be used.

摘要翻译： 本发明的目的是提供一种制造半导体器件的方法以及通过使用能够防止在TFT沟道形成区域中形成晶界的激光结晶化方法而制造的半导体器件，并且是 能够防止TFT迁移率的显着下降，导通电流的降低，以及由于晶界而导致的关断电流的增加。 形成条纹形状或矩形形状不均匀或开口。 然后将连续波激光照射到形成在绝缘膜上的半导体膜。 另外，尽管在这一点上最好使用连续波激光，但也可以使用脉波振荡激光。