公开(公告)号：US11935153B2

公开(公告)日：2024-03-19

申请号：US17135973

申请日：2020-12-28

Applicant: ATI Technologies ULC ,  Advanced Micro Devices, Inc.

Inventor： Sergey Korobkov ,  Jimshed B. Mirza ,  Anthony Hung-Cheong Chan

IPC: G06T1/60 ,  G06T1/20 ,  G06T9/00

CPC classification number: G06T1/60 ,  G06T1/20 ,  G06T9/00

Abstract: Data processing methods and devices are provided. A processing device comprises memory and a processor. The memory, which comprises a cache, is configured to store portions of data. The processor is configured to issue a store instruction to store one of the portions of data, provide identifying information associated with the one portion of data, compress the one portion of data; and store the compressed one portion of data across multiple lines of the cache using the identifying information. In an example, the one portion of data is a block of pixels and pixels and the processor is configured to request pixel data for a pixel of a compressed block of pixels, send additional requests for data for other pixels determined to belong to the compressed pixel block and provide an indication that the requests are for pixel data belonging to the compressed block of pixels.

公开(公告)号：US20240087169A1

公开(公告)日：2024-03-14

申请号：US17931499

申请日：2022-09-12

Applicant: ATI Technologies ULC

Inventor： Isabelle Elizabeth Knott

IPC: G06T9/00 ,  H04N19/70

CPC classification number: G06T9/00 ,  H04N19/70

Abstract: An apparatus and method for performing efficient video transmission. In various implementations, a computing system includes a transmitter sending a video stream to a receiver over a network. Before encoding a video frame, the transmitter identifies a first set of one or more macroblocks of the video frame that includes text. The transmitter replaces pixel color information with pixel distance information for the first set of one or more macroblocks. The transmitter inserts, in metadata information, indications that identify the first set of one or more macroblocks and specify the color values of pixels in the first set of one or more macroblocks. The transmitter encodes the video frame and sends it along with the metadata information to the receiver. The receiver uses the metadata information to reproduce the original pixel colors and maintain text clarity of an image to be depicted on a display device.

公开(公告)号：US20240071940A1

公开(公告)日：2024-02-29

申请号：US18505187

申请日：2023-11-09

Applicant: ADVANCED MICRO DEVICES, INC. ,  ATI TECHNOLOGIES ULC

Inventor： RAHUL AGARWAL ,  RAJA SWAMINATHAN ,  MICHAEL S. ALFANO ,  GABRIEL H. LOH ,  ALAN D. SMITH ,  GABRIEL WONG ,  MICHAEL MANTOR

IPC: H01L23/538 ,  H01L21/50 ,  H01L25/065 ,  H01L27/06

CPC classification number: H01L23/5384 ,  H01L21/50 ,  H01L23/5381 ,  H01L23/5385 ,  H01L25/0657 ,  H01L27/0688

Abstract: A semiconductor package includes a first die, a second die, and an interconnect die coupled to a first plurality of through-die vias in the first die and a second plurality of through-die vias in the second die. The interconnect die provides communications pathways the first die and the second die.

公开(公告)号：US20240069616A1

公开(公告)日：2024-02-29

申请号：US18461712

申请日：2023-09-06

Applicant: ADVANCED MICRO DEVICES, INC. ,  ATI TECHNOLOGIES ULC

Inventor： OLEKSANDR KHODORKOVSKY ,  STEPHEN D. PRESANT

IPC: G06F1/3206 ,  G06F1/324

CPC classification number: G06F1/3206 ,  G06F1/324 ,  Y02D10/00

Abstract: A method and apparatus controls power management of a graphics processing core when multiple virtual machines are allocated to the graphics processing core on a much finer-grain level than conventional systems. In one example, the method and apparatus processes a plurality of virtual machine power control setting requests to determine a power control request for a power management unit of a graphics processing core. The method and apparatus then controls power levels of the graphics processing core with the power management unit based on the determined power control request.

公开(公告)号：US11902532B2

公开(公告)日：2024-02-13

申请号：US17488944

申请日：2021-09-29

Applicant: ATI Technologies ULC

Inventor： Sunil Gopal Koteyar ,  Mingkai Shao

IPC: H04N19/139 ,  H04N19/126 ,  G06N20/00 ,  G06T3/40 ,  H04N19/55 ,  H04N19/142 ,  G06V20/40

CPC classification number: H04N19/139 ,  G06N20/00 ,  G06T3/40 ,  G06V20/49 ,  H04N19/126 ,  H04N19/142 ,  H04N19/55

Abstract: Systems, apparatuses, and methods for performing machine learning content categorization leveraging video encoding pre-processing are disclosed. A system includes at least a motion vector unit and a machine learning (ML) engine. The motion vector unit pre-processes a frame to determine if there is temporal locality with previous frames. If the objects of the scene have not changed by a threshold amount, then the ML engine does not process the frame, saving computational resources that would typically be used. Otherwise, if there is a change of scene or other significant changes, then the ML engine is activated to process the frame. The ML engine can then generate a QP map and/or perform content categorization analysis on this frame and a subset of the other frames of the video sequence.

公开(公告)号：US20240029488A1

公开(公告)日：2024-01-25

申请号：US18478712

申请日：2023-09-29

Applicant: Advanced Micro Devices, Inc. ,  ATI Technologies ULC

Inventor： Ashish Jain ,  Arash Moghimi

IPC: G07C9/00 ,  B60R25/24 ,  H04B17/318 ,  H04B1/7073 ,  B60R25/20 ,  G01S13/84 ,  H01Q1/32 ,  H01Q25/04 ,  H04B7/06 ,  H04W4/40 ,  G07C9/28 ,  H01Q25/00 ,  H04B7/15 ,  H04W12/122 ,  H04W12/128 ,  H04W12/64

CPC classification number: G07C9/00309 ,  B60R25/241 ,  H04B17/318 ,  H04B1/7073 ,  B60R25/2072 ,  B60R25/245 ,  G01S13/84 ,  H01Q1/3241 ,  H01Q25/04 ,  H04B7/0669 ,  H04W4/40 ,  G07C9/28 ,  H01Q25/00 ,  H04B7/15 ,  B60R25/246 ,  H04W12/122 ,  H04W12/128 ,  H04W12/64 ,  B60R2325/205 ,  G07C2009/00555 ,  G07C2209/61 ,  B60R2325/108 ,  G01S7/021

Abstract: Systems, apparatuses, and methods for implementing efficient power optimization in a computing system are disclosed. A system management unit configured to track computing activity of a computing device while processing each frame of a plurality of frames. The computing activity is tracked at least for a given period of time comprising a plurality of time slices. The system management unit further correlates a time slice associated with a given frame with a time slice associated with at least one previously processed frame from the plurality of frames, based at least in part on the tracked computing activity. The system management unit predicts a clock frequency to render the given frame, based at least in part on the correlation and renders the given frame using the predicted clock frequency.

公开(公告)号：US11863769B2

公开(公告)日：2024-01-02

申请号：US17403191

申请日：2021-08-16

Applicant: Advanced Micro Devices, Inc. ,  ATI Technologies ULC

Inventor： Lei Zhang ,  Ji Zhou ,  Zhen Chen ,  Min Yu

IPC: H04N19/159 ,  H04N19/117 ,  H04N19/187 ,  H04N19/33 ,  H04N19/423 ,  H04N19/80 ,  H04N19/59

CPC classification number: H04N19/423 ,  H04N19/117 ,  H04N19/159 ,  H04N19/187 ,  H04N19/33 ,  H04N19/59 ,  H04N19/80

Abstract: A system configured to perform scalable video encoding is provided. The system includes a memory; and a processing unit, wherein the processing unit is configured to: receive inter-layer data and a current picture, wherein the current picture has a base layer; upsample the inter-layer data to generate residual data and reconstruction data, wherein the inter-layer data includes a base mode flag; and encode the current picture to an enhanced layer using the upsampled inter-layer data based on a block type of the base layer and the base mode flag.

公开(公告)号：US11862066B2

公开(公告)日：2024-01-02

申请号：US17706790

申请日：2022-03-29

Applicant: ATI TECHNOLOGIES ULC

Inventor： Anthony W L Koo ,  Syed Athar Hussain

IPC: G09G5/00 ,  G09G3/20 ,  G09G5/36

CPC classification number: G09G3/2096 ,  G09G5/006 ,  G09G5/363 ,  G09G2310/08 ,  G09G2320/0247 ,  G09G2320/10 ,  G09G2320/103 ,  G09G2340/0435 ,  G09G2360/18

Abstract: A graphics processing unit (GPU) instructs a display control module to capture content and display captured content in response to the refresh rate of a display exceeding a frame generation rate of the GPU. Rather than re-transmit the same frame multiple times, the GPU instructs the display control module to replay a previously-transmitted frame. During a refresh cycle in which the display control module is replaying captured content, the GPU omits accessing memory to retrieve and resend the frame that is being replayed, and instead sends only invalid data and GPU timing information so that the display control module remains synchronized with the GPU.

公开(公告)号：US11861781B2

公开(公告)日：2024-01-02

申请号：US17134744

申请日：2020-12-28

Applicant: ADVANCED MICRO DEVICES, INC. ,  ATI TECHNOLOGIES ULC ,  SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sreekanth Godey ,  Ashkan Hosseinzadeh Namin ,  Seunghun Jin ,  Teik-Chung Tan

IPC: G06F1/3228 ,  G06T15/00 ,  G06F1/3212 ,  G06F9/50 ,  G06F1/3215 ,  G06F9/30

CPC classification number: G06T15/005 ,  G06F1/3212 ,  G06F1/3215 ,  G06F1/3228 ,  G06F9/30098 ,  G06F9/5011

Abstract: The graphics processing unit (GPU) of a processing system transitions to a low-power state between frame rendering operations according to an inter-frame power off process, where GPU state information is stored on retention hardware. The retention hardware can include retention random access memory (RAM) or retention flip-flops. The retention hardware is operable in an active mode and a retention mode, where read/write operations are enabled at the retention hardware in the active mode and disabled in the retention mode, but data stored on the retention hardware is still retained in the retention mode. The retention hardware is placed in the retention state between frame rendering operations. The GPU transitions from its low-power state to its active state upon receiving an indication that a new frame is ready to be rendered and is restored using the GPU state information stored at the retention hardware.

公开(公告)号：US20230420018A1

公开(公告)日：2023-12-28

申请号：US17849197

申请日：2022-06-24

Applicant: ATI Technologies ULC ,  Advanced Micro Devices, Inc.

Inventor： Xuan Chen ,  Chih-Hua Hsu ,  Pradeep Jayaraman ,  Abdussalam Aburwein

IPC: G11C7/22 ,  G11C7/10 ,  G11C8/18 ,  G11C5/02

CPC classification number: G11C7/222 ,  G11C7/1063 ,  G11C7/109 ,  G11C8/18 ,  G11C5/025

Abstract: A data processor is for accessing a memory having a first pseudo channel and a second pseudo channel. The data processor includes at least one memory accessing agent, a memory controller, and a data fabric. The at least one memory accessing agent generates generating memory access requests including first memory access requests that access the memory. The memory controller provides memory commands to the memory in response to the first memory access requests. The data fabric routes the first memory access requests to a first downstream port in response to a corresponding first memory request accessing the first pseudo channel, and to a second downstream port in response to the corresponding first memory request accessing the second pseudo channel. The memory controller has first and second upstream ports coupled to the first and second downstream ports of the data fabric, respectively, and a downstream port coupled to the memory.