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    Nonvolatile memory and method of erasing for nonvolatile memory
    62.
    发明授权
    Nonvolatile memory and method of erasing for nonvolatile memory 有权

    公开(公告)号：US07068541B2

    公开(公告)日：2006-06-27

    申请号：US10700592

    申请日：2003-11-05

    申请人： Yoshinori Sakamoto ,  Tatsuya Bando

    发明人： Yoshinori Sakamoto ,  Tatsuya Bando

    IPC分类号： G11C11/34

    CPC分类号： G11C16/3477 ,  G11C16/16

    摘要： The number of rewrites for memory cells is to be increased, and the reliability of data reading to be substantially improved. Where data in memory cells are to be erased, the switching of an erase voltage to be applied to the control gate of each memory cell, while switching from one to another of voltages of any different levels, as the control gate voltage (=soft erase voltage) is accomplished according to the quantity of electric charges accumulated at the floating gate of each memory cell so as to keep substantially constant the voltage applied to the tunnel film of the memory cell. Upon acceptance of an erase command, a CPU supplies a control signal to a decoder, and on the basis of the resultant decode signal an erase voltage switching circuit generates a soft erase voltage of a certain level. After that, while switching from one to another of soft erase voltages differing in level, data in the memory cell are erased. Upon completion of erasing data in the memory cell, erase verification is carried out.

    Non-volatile semiconductor memory device and erasing control method thereof
    63.
    发明授权
    Non-volatile semiconductor memory device and erasing control method thereof 失效
    非易失性半导体存储器件及其擦除控制方法

    公开(公告)号：US07038951B2

    公开(公告)日：2006-05-02

    申请号：US10866442

    申请日：2004-06-10

    申请人： Yasuaki Hirano ,  Shuichiro Kouchi

    发明人： Yasuaki Hirano ,  Shuichiro Kouchi

    IPC分类号： G11C16/04

    CPC分类号： G11C16/3477 ,  G11C16/16 ,  G11C16/3445 ,  G11C16/3459 ,  G11C16/3468

    摘要： A non-volatile semiconductor memory device includes a memory cell array including a plurality of memory cells, wherein information is writable to each of the plurality of memory cells and information is erasable from each of the plurality of memory cells, and the plurality of memory cells are grouped into at least one memory block; and a write and erasing section for performing a program write operation to a prescribed memory cell in one memory block in a prescribed voltage condition and for performing an erasing operation with respect to the memory cells in the one memory block, wherein the write and erasing section performs a pre-erasing write operation to the memory cells in the one memory block in a voltage condition, which is different from the prescribed voltage condition, before the erasing operation is performed with respect to the memory cells in the one memory block.

    摘要翻译： 非挥发性半导体存储器件包括存储单元阵列，该存储单元阵列包括多个存储单元，其中信息可写入多个存储单元中的每一个，并且信息可从多个存储单元中的每一个擦除，并且多个存储单元 被分组成至少一个存储块; 以及写入和擦除部分，用于以规定的电压条件对一个存储器块中的规定的存储器单元执行程序写入操作，并且对于所述一个存储器块中的存储器单元执行擦除操作，其中写入和擦除部分 在相对于一个存储块中的存储单元执行擦除操作之前，在与规定电压条件不同的电压条件下，对一个存储块中的存储单元执行预擦除写入操作。

    Group erasing system for flash array with multiple sectors
    66.
    发明授权
    Group erasing system for flash array with multiple sectors 有权
    具有多个扇区的闪存阵列的组擦除系统

    公开(公告)号：US06940759B2

    公开(公告)日：2005-09-06

    申请号：US10685957

    申请日：2003-10-14

    申请人： Sai K. Tsang ,  Steven J. Schumann ,  Fai Ching

    发明人： Sai K. Tsang ,  Steven J. Schumann ,  Fai Ching

    IPC分类号： G11C8/10 ,  G11C8/12 ,  G11C11/34 ,  G11C16/00 ,  G11C16/16

    CPC分类号： G11C16/16 ,  G11C8/10 ,  G11C8/12 ,  G11C16/3477

    摘要： A decoding system for multi-plane memories routes address information corresponding to distinct memory access operations to the designated planes. The system includes an array of functional registers dedicated to random access read, burst read, program, erase, and erase-suspend program operations. Plane selector blocks for each plane receive the address outputs from all of the registers and plane function select logic controls the routing in accord with memory access commands for specified planes. Simultaneous operations of different type in different planes and nested operations in the same plane are possible.

    摘要翻译： 用于多平面存储器的解码系统将对应于不同存储器访问操作的地址信息路由到指定的平面。 该系统包括专用于随机访问读取，突发读取，编程，擦除和擦除 - 挂起程序操作的功能寄存器阵列。 每个平面的平面选择器块接收所有寄存器的地址输出，平面函数选择逻辑根据指定平面的存储器访问命令控制路由。 同一平面内不同类型的同时操作和嵌套操作是可能的。

    Flash memory device capable of preventing an over-erase of flash memory cells and erase method thereof
    67.
    发明授权
    Flash memory device capable of preventing an over-erase of flash memory cells and erase method thereof 有权
    能够防止闪存单元的过擦除及其擦除方法的闪存装置

    公开(公告)号：US06914827B2

    公开(公告)日：2005-07-05

    申请号：US10430364

    申请日：2003-05-05

    申请人： Ki-Hwan Choi

    发明人： Ki-Hwan Choi

    IPC分类号： G11C11/34 ,  G11C16/34 ,  G11C7/00

    CPC分类号： G11C16/3418 ,  G11C16/3468 ,  G11C16/3477

    摘要： The flash memory device according to the present invention includes an erase control circuit, used as a state machine, having embodied erase algorithm which can prevent flash memory cells from being over-erased. The erase control circuit, first, checks whether or not threshold voltages of selected cells reach a predetermined pre-verify voltage higher than the maximum value of a target threshold voltage range corresponding to the erased state. When at least one of the selected cells has its threshold voltage higher than the pre-verify voltage, a high voltage generator generates a bulk voltage that is increased step by step by a predetermined voltage level. And, when the selected cells all have threshold voltages equal to or less than the pre-verify voltage, the high voltage generator generates a constant bulk voltage. According to this bulk voltage control scheme, the number of flash memory cells over-erased at the erase operation is reduced reducing the total erase time.

    摘要翻译： 根据本发明的闪速存储器件包括用作状态机的具有实现的擦除算法的擦除控制电路，其可以防止闪速存储器单元被过度擦除。 擦除控制电路首先检查所选择的单元的阈值电压是否达到比对应于擦除状态的目标阈值电压范围的最大值高的预定预验证电压。 当所选择的单元中的至少一个具有高于预验证电压的阈值电压时，高电压发生器产生逐步增加预定电压电平的体电压。 并且，当所选择的单元都具有等于或小于预验证电压的阈值电压时，高电压发生器产生恒定的体电压。 根据该体电压控制方案，在擦除操作时被擦除的闪存单元的数量减少，减少了总擦除时间。

    Weak programming method of non-volatile memory
    68.
    发明授权
    Weak programming method of non-volatile memory 有权
    非易失性存储器编程方法薄弱

    公开(公告)号：US06862219B2

    公开(公告)日：2005-03-01

    申请号：US10249140

    申请日：2003-03-19

    申请人： Shih-Hsien Yang ,  Chien-Min Wu ,  James Juen Hsu ,  Chi-Moon Huang

    发明人： Shih-Hsien Yang ,  Chien-Min Wu ,  James Juen Hsu ,  Chi-Moon Huang

    IPC分类号： G11C11/34 ,  G11C16/04 ,  G11C16/34

    CPC分类号： G11C16/3477 ,  G11C16/3404 ,  G11C16/3409

    摘要： A weak programming method of a non-volatile memory. A first voltage is applied to a substrate during a first duration, while a control-gate voltage, such as zero volt, is applied to the gate, such that the leakage of the bit line is reduced and electron-hole pairs are generated. In the second duration, a second voltage is applied to the substrate, and a third voltage is applied to the gate to enhance the capability of injecting electrons into the floating gate of the non-volatile memory. Therefore, the distribution of the threshold voltage is more concentrated. The second voltage has a polarity the same as that of the first voltage, while the polarity of the third voltage is opposite to that of the second voltage.

    摘要翻译： 非易失性存储器的弱编程方法。 在第一持续时间内将第一电压施加到衬底，同时将诸如零伏特的控制栅极电压施加到栅极，使得位线的泄漏减小并且产生电子 - 空穴对。 在第二持续时间中，向衬底施加第二电压，并且向栅极施加第三电压以增强将电子注入非易失性存储器的浮动栅极的能力。 因此，阈值电压的分布更为集中。 第二电压具有与第一电压相同的极性，而第三电压的极性与第二电压的极性相反。

    Nonvolatile semiconductor memory
    70.
    发明申请
    Nonvolatile semiconductor memory 有权

    公开(公告)号：US20040141378A1

    公开(公告)日：2004-07-22

    申请号：US10756267

    申请日：2004-01-14

    申请人： Kabushiki Kaisha Toshiba

    发明人： Toru Tanzawa ,  Tadayuki Taura ,  Masao Kuriyama

    IPC分类号： G11C011/34

    CPC分类号： G11C16/107 ,  G11C16/30 ,  G11C16/3409 ,  G11C16/344 ,  G11C16/3445 ,  G11C16/3459 ,  G11C16/3477

    摘要： A potential generating circuit generates two types of erase verify threshold values EVT1 and EVT2. These values satisfy the relationship of EVT2nullEVT1null(OEVTnullEVTL). OEVT is an over-erase verify threshold value. While the erase verify threshold value is set at EVT2, the lower limit of a threshold voltage distribution after data erase is higher than OEVT. EVTL is the lower limit of the threshold voltage distribution after data erase while the erase verify threshold value is set at EVT1 and is lower than OEVT. The erase verify threshold values EVT1 and EVT2 are switched according to an operation mode. During a write/erase test, for example, the erase verify threshold value is set at EVT2. On the other hand, during the normal operation, the erase verify threshold value is set at EVT1.