公开(公告)号：US20090323395A1

公开(公告)日：2009-12-31

申请号：US12409958

申请日：2009-03-24

申请人： Yoshihiro UEDA

发明人： Yoshihiro UEDA

IPC分类号： G11C11/00 ,  G11C5/14 ,  G11C7/10

CPC分类号： G11C11/56 ,  G11C13/00 ,  G11C13/004 ,  G11C2013/0054 ,  G11C2211/5631 ,  G11C2213/72

摘要： A plurality of memory cells, each including a variable resistance element capable of having four or more values, are arranged at intersections of first wirings and second wirings. A control circuit selectively drives the first and second wirings. A sense amplifier circuit compares, with a reference voltage, a voltage generated by a current flowing through a selected memory cell. A reference voltage generation circuit includes: a resistance circuit including first and second resistive elements connected in parallel. Each of the first resistive elements has a resistance value substantially the same as a maximum resistance value in the variable resistance elements, and each of the second resistive elements has a resistance value substantially the same as a minimum resistance value in the variable resistance elements. A current regulator circuit averages currents flowing through the first and second resistive elements.

摘要翻译： 在第一布线和第二布线的交点处布置有多个存储单元，每个存储单元包括能够具有四个或更多个值的可变电阻元件。 控制电路选择性地驱动第一和第二布线。 读出放大器电路与参考电压比较由流过所选存储单元的电流产生的电压。 参考电压产生电路包括：电阻电路，包括并联连接的第一和第二电阻元件。 每个第一电阻元件具有与可变电阻元件中的最大电阻值基本相同的电阻值，并且每个第二电阻元件具有与可变电阻元件中的最小电阻值基本相同的电阻值。 电流调节器电路平均流过第一和第二电阻元件的电流。

公开(公告)号：US20080002457A1

公开(公告)日：2008-01-03

申请号：US11761864

申请日：2007-06-12

申请人： Haruki Toda ,  Koichi Kubo

发明人： Haruki Toda ,  Koichi Kubo

IPC分类号： G11C11/00

CPC分类号： G11C13/0007 ,  G11C11/5678 ,  G11C11/5685 ,  G11C13/0004 ,  G11C13/004 ,  G11C13/0069 ,  G11C2013/0054 ,  G11C2013/0092 ,  G11C2211/5622 ,  G11C2211/5631 ,  G11C2213/31 ,  G11C2213/71 ,  G11C2213/72 ,  H01L27/2409 ,  H01L27/2472 ,  H01L27/2481 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/147

摘要： A resistance change memory device including a substrate, first and second wiring lines formed above the substrate to be insulated from each other and memory cells disposed between the first and second wiring lines, wherein the memory cell includes: a variable resistance element for storing as information a resistance value; and a Schottky diode connected in series to the variable resistance element. The variable resistance element has a recording layer formed of a first composite compound expressed by AxMyOz (where “A” and “M” are cation elements different from each other; “O” oxygen; and 0.5≦x≦1.5, 0.5≦y≦2.5 and 1.5≦z≦4.5) and a second composite compound containing at least one transition element and a cavity site for housing a cation ion.

摘要翻译： 一种电阻变化存储装置，包括基板，形成在基板上方以彼此绝缘的第一和第二布线以及设置在第一和第二布线之间的存储单元，其中存储单元包括：可变电阻元件，用于存储为信息 电阻值 和与可变电阻元件串联连接的肖特基二极管。 可变电阻元件具有由第一复合化合物形成的记录层，由第一复合化合物（其中“A”和“ M“是彼此不同的阳离子元素;”O“氧;和0.5≤x≤1.5,0.5≤y≤2.5和1.5≤z≤4.5）和含有至少一个转变的第二复合化合物 元件和用于容纳阳离子离子的空腔部位。

公开(公告)号：US20080002456A1

公开(公告)日：2008-01-03

申请号：US11761823

申请日：2007-06-12

申请人： Haruki Toda ,  Koichi Kubo

发明人： Haruki Toda ,  Koichi Kubo

IPC分类号： G11C11/00

CPC分类号： G11C13/0007 ,  G11C11/5678 ,  G11C11/5685 ,  G11C13/0004 ,  G11C13/004 ,  G11C13/0069 ,  G11C2013/0054 ,  G11C2013/0092 ,  G11C2211/5622 ,  G11C2211/5631 ,  G11C2213/31 ,  G11C2213/71 ,  G11C2213/72 ,  H01L27/2409 ,  H01L27/2472 ,  H01L27/2481 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/126 ,  H01L45/147

摘要： A resistance change memory device including a substrate, first and second wiring lines formed above the substrate to be insulated from each other, and memory cells disposed between the first and second wiring lines wherein the memory cell includes, a variable resistance element for storing as information a resistance value and a Schottky diode connected in series to the variable resistance element. The variable resistance element has a recording layer composed of a composite compound containing at least two types of cation elements, at least one type of the cation element being a transition element having “d”-orbit, in which electrons are incompletely filled, the shortest distance between adjacent cation elements being 0.32 nm or less.

摘要翻译： 一种电阻变化存储装置，包括：基板，形成在所述基板上方彼此绝缘的第一和第二布线;以及设置在所述第一和第二布线之间的存储单元，其中所述存储单元包括：可变电阻元件，用于存储为信息 电阻值和与可变电阻元件串联连接的肖特基二极管。 可变电阻元件具有由包含至少两种阳离子元素的复合化合物构成的记录层，至少一种阳离子元素是具有“d” - 轨道的过渡元素，其中电子未完全填充，最短 相邻阳离子元素之间的距离为0.32nm以下。

公开(公告)号：US5995412A

公开(公告)日：1999-11-30

申请号：US167192

申请日：1998-10-06

申请人： Yoshiji Ohta

发明人： Yoshiji Ohta

IPC分类号： G11C16/02 ,  G11C11/56 ,  G11C16/04 ,  G11C16/06

CPC分类号： G11C11/5628 ,  G11C11/5621 ,  G11C11/5642 ,  G11C2211/5624 ,  G11C2211/5631 ,  G11C2211/5642

摘要： A nonvolatile semiconductor storage device and writing method thereof are capable of concurrently executing a write operation and a verify operation of multi-value data into a plurality of memory cells and writing multi-value data at high speed. Latch circuits of Latch0 and Latch1 store an input multi-value data to be written into a memory cell selected by a bit line and a word line. Multi-value sense amplifiers read the multi-value data written in the memory cell. Based on the input multi-value data (latch nodes Q0#, Q1#) stored in the latch circuits of Latch0 and Latch1 and the multi-value data (sense nodes S0#, S1#) read from the memory cell by the multi-value sense amplifiers, a bit line voltage generating circuit applies a specified voltage for writing the input multi-value data into the memory cell to the bit line connected to the memory cell.

摘要翻译： 非易失性半导体存储装置及其写入方法能够将多值数据的写入操作和验证操作同时执行到多个存储单元中，并以高速写入多值数据。 Latch0和Latch1的锁存电路存储要写入由位线和字线选择的存储单元的输入多值数据。 多值读出放大器读取写入存储单元的多值数据。 基于存储在Latch0和Latch1的锁存电路中的输入多值数据（锁存节点Q0＃，Q1＃）和通过多存储器从存储器单元读取的多值数据（感测节点S0＃，S1＃）， 值读出放大器，位线电压产生电路将用于将输入的多值数据写入存储单元的指定电压施加到连接到存储单元的位线。

公开(公告)号：US5909390A

公开(公告)日：1999-06-01

申请号：US991650

申请日：1997-12-16

申请人： Eliyahou Harari

发明人： Eliyahou Harari

IPC分类号： G11C11/56 ,  G11C16/04 ,  G11C16/34 ,  G11C29/00 ,  H01L21/28 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  G11C7/00

CPC分类号： H01L27/11519 ,  G11C11/5621 ,  G11C11/5628 ,  G11C11/5635 ,  G11C11/5642 ,  G11C16/0425 ,  G11C16/349 ,  G11C16/3495 ,  G11C29/765 ,  G11C29/82 ,  H01L21/28273 ,  H01L27/115 ,  H01L27/11517 ,  H01L29/7881 ,  H01L29/7885 ,  G11C2211/5613 ,  G11C2211/5631 ,  G11C2211/5634 ,  G11C2211/5644 ,  G11C29/00

摘要： A memory system made up of electrically programmable read only memory (EPROM) or flash electrically erasable and programmable read only memory (EEPROM) cells. An intelligent programming technique allows each memory cell to store more than the usual one bit of information. More than one bit is stored in a cell by establishing more than two distinct threshold states into which the cell is programmed. A series of pulses of increasing voltage is applied to each addressed memory cell during its programming, the state of the cell being read in between pulses. The pulses are terminated upon the addressed cell reaching its desired state or a preset maximum number of pulses has been reached. An intelligent erase algorithm prolongs the useful life of the memory cells. A series of pulses is also applied to a block of cells being erased, the state of at least a sample number of cells being read in between pulses. The erasing process is stopped when the cells being read are determined to have reached a fully erased state or one of a number of other conditions has occurred. Individual records of the number of erase cycles experienced by blocks of flash EEPROM cells are kept, preferable as part of the blocks themselves, in order to maintain an endurance history of the cells within the blocks. Use of these various features provides a memory having a very high storage density and a long life, making it particularly useful as a solid state memory in place of magnetic disk storage devices in computer systems.

摘要翻译： 由电可编程只读存储器（EPROM）或闪存电可擦除和可编程只读存储器（EEPROM）单元组成的存储器系统。 智能编程技术允许每个存储器单元存储比通常的一位信息。 通过建立单元被编程的两个以上不同的阈值状态，多个位被存储在单元中。 在其编程期间，一系列增加电压的脉冲被施加到每个寻址的存储器单元，在脉冲之间读取单元的状态。 脉冲在所寻址的单元达到其期望状态时终止，或达到预设的最大脉冲数。 智能擦除算法可延长存储单元的使用寿命。 一系列脉冲也被施加到被擦除的单元块，在脉冲之间读取至少一个单元的样本数的状态。 当读取的单元被确定为已经达到完全擦除状态或者已经发生了许多其他条件中的一种时，停止擦除过程。 保存快闪EEPROM单元块所经历的擦除周期数的个别记录，优选作为块本身的一部分，以便保持块内的单元的耐久性历史。 使用这些各种特征提供了具有非常高的存储密度和长寿命的存储器，使得其作为固态存储器代替计算机系统中的磁盘存储装置是特别有用的。

公开(公告)号：US5838612A

公开(公告)日：1998-11-17

申请号：US869072

申请日：1997-06-04

申请人： Cristiano Calligaro ,  Vincenzo Daniele ,  Roberto Gastaldi ,  Alessandro Manstretta ,  Nicola Telecco ,  Guido Torelli

发明人： Cristiano Calligaro ,  Vincenzo Daniele ,  Roberto Gastaldi ,  Alessandro Manstretta ,  Nicola Telecco ,  Guido Torelli

IPC分类号： G11C17/00 ,  G11C11/56 ,  G11C16/02 ,  G11C16/06 ,  G11C11/34

CPC分类号： G11C11/5642 ,  G11C11/5621 ,  G11C2211/5631

摘要： Reading circuit for multilevel non-volatile memory cell devices having, for each cell to be read, a selection line with which is associated a load and a decoupling and control stage with a feedback loop which stabilizes the voltage on a circuit node of the selection line. To this node are connected a current replica circuit which are controlled by the feedback loop. These include loads and circuit elements homologous to those associated with the selection line of the memory cell and have an output interface circuit for connection to current comparator circuit.

摘要翻译： 用于多电平非易失性存储单元器件的读取电路，对于要读取的每个单元，具有与负载和去耦合和控制级相关联的选择线，其具有稳定选择线的电路节点上的电压的反馈环路 。 对该节点连接由反馈回路控制的当前复制电路。 这些包括与与存储器单元的选择线相关的负载和电路元件同源的负载和电路元件，并且具有用于连接到电流比较器电路的输出接口电路。

公开(公告)号：US5815443A

公开(公告)日：1998-09-29

申请号：US634953

申请日：1996-04-19

申请人： Sherif Sweha ,  Mark E. Bauer

发明人： Sherif Sweha ,  Mark E. Bauer

IPC分类号： G11C16/06 ,  G11C8/00 ,  G11C11/56 ,  G11C16/02 ,  G11C7/00

CPC分类号： G11C11/5621 ,  G11C11/5628 ,  G11C11/5635 ,  G11C11/5642 ,  G11C16/08 ,  G11C2211/5631 ,  G11C2211/5632 ,  G11C2211/5642 ,  G11C8/00

摘要： Sense path and write path architectures for read and write accesses of a memory device having memory cells that store n binary bits are disclosed. "By-output" architectures provide one output per bit such that each selected memory cell is mapped to n outputs and the n bits stored in the selected memory cell are read in parallel. "By-address" architectures provide one address per bit such that each selected memory cell is mapped to one output, and the n bits stored in the selected memory cell are read sequentially.

公开(公告)号：US5568439A

公开(公告)日：1996-10-22

申请号：US468061

申请日：1995-06-06

申请人： Eliyahou Harari

发明人： Eliyahou Harari

IPC分类号： G11C11/56 ,  G11C16/04 ,  G11C16/34 ,  G11C29/00 ,  H01L21/28 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  G11C16/06 ,  G06F11/20

CPC分类号： H01L27/11519 ,  G11C11/5621 ,  G11C11/5628 ,  G11C11/5635 ,  G11C11/5642 ,  G11C16/0425 ,  G11C16/349 ,  G11C16/3495 ,  G11C29/765 ,  G11C29/82 ,  H01L21/28273 ,  H01L27/115 ,  H01L27/11517 ,  H01L29/7881 ,  H01L29/7885 ,  G11C2211/5613 ,  G11C2211/5631 ,  G11C2211/5634 ,  G11C2211/5644 ,  G11C29/00

摘要： A memory system made up of electrically programmable read only memory (EPROM) or flash electrically erasable and programmable read only memory (EEPROM) cells. An intelligent programming technique allows each memory cell to store more than the usual one bit of information. More than one bit is stored in a cell by establishing more than two distinct threshold states into which the cell is programmed. A series of pulses of increasing voltage is applied to each addressed memory cell during its programming, the state of the cell being read in between pulses. The pulses are terminated upon the addressed cell reaching its desired state or a preset maximum number of pulses has been reached. An intelligent erase algorithm prolongs the useful life of the memory cells. A series of pulses is also applied to a block of cells being erased, the state of at least a sample number of cells being read in between pulses. The erasing process is stopped when the cells being read are determined to have reached a fully erased state or one of a number of other conditions has occurred. Individual records of the number of erase cycles experienced by blocks of flash EEPROM cells are kept, preferable as part of the blocks themselves, in order to maintain an endurance history of the cells within the blocks. Use of these various features provides a memory having a very high storage density and a long life, making it particularly useful as a solid state memory in place of magnetic disk storage devices in computer systems.

摘要翻译： 由电可编程只读存储器（EPROM）或闪存电可擦除和可编程只读存储器（EEPROM）单元组成的存储器系统。 智能编程技术允许每个存储器单元存储比通常的一位信息。 通过建立单元被编程的两个以上不同的阈值状态，多个位被存储在单元中。 在其编程期间，一系列增加电压的脉冲被施加到每个寻址的存储器单元，在脉冲之间读取单元的状态。 脉冲在所寻址的单元达到其期望状态时终止，或达到预设的最大脉冲数。 智能擦除算法可延长存储单元的使用寿命。 一系列脉冲也被施加到被擦除的单元块，在脉冲之间读取至少一个单元的样本数的状态。 当读取的单元被确定为已经达到完全擦除状态或者已经发生了许多其他条件中的一种时，停止擦除过程。 保存快闪EEPROM单元块所经历的擦除周期数的个别记录，优选作为块本身的一部分，以便保持块内的单元的耐久性历史。 使用这些各种特征提供了具有非常高的存储密度和长寿命的存储器，使得其作为固态存储器代替计算机系统中的磁盘存储装置是特别有用的。

公开(公告)号：US5293560A

公开(公告)日：1994-03-08

申请号：US970949

申请日：1992-11-03

申请人： Eliyahou Harari

发明人： Eliyahou Harari

IPC分类号： G11C11/56 ,  G11C16/04 ,  G11C16/34 ,  G11C29/00 ,  H01L21/28 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788

CPC分类号： H01L27/11519 ,  G11C11/5621 ,  G11C11/5628 ,  G11C11/5635 ,  G11C11/5642 ,  G11C16/0425 ,  G11C16/349 ,  G11C16/3495 ,  G11C29/765 ,  G11C29/82 ,  H01L21/28273 ,  H01L27/115 ,  H01L27/11517 ,  H01L29/7881 ,  H01L29/7885 ,  G11C2211/5613 ,  G11C2211/5631 ,  G11C2211/5634 ,  G11C2211/5644 ,  G11C29/00

摘要： A memory system made up of electrically programmable read only memory (EPROM) or flash electrically erasable and programmable read only memory (EEPROM) cells. An intelligent programming technique allows each memory cell to store more than the usual one bit of information. More than one bit is stored in a cell by establishing more than two distinct threshold states into which the cell is programmed. A series of pulses of increasing voltage is applied to each addressed memory cell during its programming, the state of the cell being read in between pulses. The pulses are terminated upon the addressed cell reaching its desired state or a preset maximum number of pulses has been reached. An intelligent erase algorithm prolongs the useful life of the memory cells. A series of pulses is also applied to a block of cells being erased, the state of at least a sample number of cells being read in between pulses. The erasing process is stopped when the cells being read are determined to have reached a fully erased state or one of a number of other conditions has occurred. Use of these various features provides a memory having a very high storage density and a long life, making it particularly useful as a solid state memory in place of magnetic disk storage devices in computer systems.

摘要翻译： 由电可编程只读存储器（EPROM）或闪存电可擦除和可编程只读存储器（EEPROM）单元组成的存储器系统。 智能编程技术允许每个存储器单元存储比通常的一位信息。 通过建立单元被编程的两个以上不同的阈值状态，多个位被存储在单元中。 在其编程期间，一系列增加电压的脉冲被施加到每个寻址的存储器单元，在脉冲之间读取单元的状态。 脉冲在所寻址的单元达到其期望状态时终止，或达到预设的最大脉冲数。 智能擦除算法可延长存储单元的使用寿命。 一系列脉冲也被施加到被擦除的单元块，在脉冲之间读取至少一个单元的样本数的状态。 当读取的单元被确定为已经达到完全擦除状态或者已经发生了许多其他条件中的一种时，停止擦除过程。 使用这些各种特征提供了具有非常高的存储密度和长寿命的存储器，使得其作为固态存储器代替计算机系统中的磁盘存储装置是特别有用的。

公开(公告)号：US5268318A

公开(公告)日：1993-12-07

申请号：US776826

申请日：1991-10-15

申请人： Eliyahou Harari

发明人： Eliyahou Harari

IPC分类号： G11C11/56 ,  G11C16/04 ,  G11C16/34 ,  G11C29/00 ,  H01L21/28 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/60

CPC分类号： H01L27/11519 ,  G11C11/5621 ,  G11C11/5628 ,  G11C11/5635 ,  G11C11/5642 ,  G11C16/0425 ,  G11C16/349 ,  G11C16/3495 ,  G11C29/765 ,  G11C29/82 ,  H01L21/28273 ,  H01L27/115 ,  H01L27/11517 ,  H01L29/7881 ,  H01L29/7885 ,  G11C2211/5613 ,  G11C2211/5631 ,  G11C2211/5634 ,  G11C2211/5644 ,  G11C29/00 ,  Y10S438/972

摘要： Structures, methods of manufacturing and methods of use of electrically programmable read only memories (EPROM) and flash electrically erasable and programmable read only memories (EEPROM) include split channel and other cell configurations. An arrangement of elements and cooperative processes of manufacture provide self-alignment of the elements. An intelligent programming technique allows each memory cell to store more than the usual one bit of information. An intelligent erase algorithm prolongs the useful life of the memory cells. Use of these various features provides a memory having a very high storage density and a long life, making it particularly useful as a solid state memory in place of magnetic disk storage devices in computer systems.