公开(公告)号：US07515434B2

公开(公告)日：2009-04-07

申请号：US11014962

申请日：2004-12-20

Applicant: Aneta Wyrzykowska ,  Herman Kwong ,  Kah Ming Soh

Inventor： Aneta Wyrzykowska ,  Herman Kwong ,  Kah Ming Soh

IPC: H05K1/18

CPC classification number: H05K1/0246 ,  H01L2224/16225 ,  H05K1/023 ,  H05K1/141 ,  H05K1/16 ,  H05K1/162 ,  H05K1/165 ,  H05K1/167 ,  H05K1/184 ,  H05K3/4046 ,  H05K3/4053 ,  H05K2201/0187 ,  H05K2201/10045 ,  H05K2201/10545 ,  H05K2201/10636 ,  H05K2201/10734 ,  Y02P70/611

Abstract: A technique for enhancing circuit density and performance is disclosed. In one particular exemplary embodiment, the technique may be realized as a method for enhancing circuit density and performance of a microelectronic module. The method may comprise forming a discrete package, wherein the discrete package comprises one or more passive devices that are desirable for the performance of the microelectronic module. The method may also comprise coupling the discrete package to the microelectronic module.

Abstract translation: 公开了一种用于增强电路密度和性能的技术。 在一个特定的示例性实施例中，该技术可以被实现为用于增强微电子模块的电路密度和性能的方法。 该方法可以包括形成分立封装，其中分立封装包括对微电子模块执行所期望的一个或多个无源器件。 该方法还可以包括将分立封装耦合到微电子模块。

公开(公告)号：US20080136580A1

公开(公告)日：2008-06-12

申请号：US11947422

申请日：2007-11-29

Applicant: Hyo-Jae BANG ,  Dong-Chun LEE ,  Seong-Chan HAN ,  Jung-Hyeon KIM ,  Hyun-Seok CHOI

Inventor： Hyo-Jae BANG ,  Dong-Chun LEE ,  Seong-Chan HAN ,  Jung-Hyeon KIM ,  Hyun-Seok CHOI

IPC: H01C1/01

CPC classification number: H01C1/144 ,  H01C1/01 ,  H01C7/18 ,  H05K3/3436 ,  H05K3/3442 ,  H05K2201/09172 ,  H05K2201/10045 ,  Y02P70/613

Abstract: Provided are a chip network resistor contacting a printed circuit board (PCB) through solder balls and a semiconductor module having the chip network resistor. The chip network resistor includes: a body formed of an insulating material; a resistor formed on the body; external electrodes connected to the resistor and disposed on a lower surface of the body so as to have solder ball pad shapes; and conductive balls adhered on the external electrodes.

Abstract translation: 提供了通过焊球与印刷电路板（PCB）接触的芯片网络电阻器和具有芯片网络电阻器的半导体模块。 芯片网络电阻器包括：由绝缘材料形成的主体; 形成在体上的电阻; 外部电极连接到电阻器并且设置在主体的下表面上以具有焊球形状; 并且导电球附着在外部电极上。

公开(公告)号：US20070076392A1

公开(公告)日：2007-04-05

申请号：US11513034

申请日：2006-08-31

Applicant: Kazuhiro Urashima ,  Shinji Yuri ,  Manabu Sato ,  Kohki Ogawa

Inventor： Kazuhiro Urashima ,  Shinji Yuri ,  Manabu Sato ,  Kohki Ogawa

IPC: H05K1/18

CPC classification number: H05K1/185 ,  H01G2/06 ,  H01G4/40 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/49822 ,  H01L23/49838 ,  H01L24/81 ,  H01L2221/68345 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/81192 ,  H01L2224/81801 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01038 ,  H01L2924/01042 ,  H01L2924/01047 ,  H01L2924/01056 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/351 ,  H05K1/0233 ,  H05K1/0234 ,  H05K3/4602 ,  H05K2201/10045 ,  H05K2201/10674 ,  H05K2201/10712 ,  H01L2924/00 ,  H01L2224/05599

Abstract: A wiring board comprising: a board core (11) having a core main surface (12) and a core reverse surface (13); a capacitor (101, 101A, 101B, 101C, 101D, 101E, 101F, 101G, 101H, 101J, 1101, 1101′, 1101″, 1101′″, 1101″″, 1101′″″) having a capacitor main surface (102) and a capacitor reverse surface (103) and having a structure in which first inner electrode layers (141) and second inner electrode layers (142) are alternately laminated and arranged via a dielectric layer (105), the capacitor (101, 101A, 101B, 101C, 101D, 101E, 101F, 101G, 101H, 101J, 1101, 1101′, 1101″, 1101′″, 1101″″, 1101′″″) being accommodated in the board core (11) in a state in which the core main surface (12) and the capacitor main surface (102) are oriented on a same side; and a wiring laminated portion (31) having a structure in which interlayer insulating layers (33, 35) and conductor layers (42) are alternately laminated on the core main surface (12) and the capacitor main surface (102), wherein an inductor (251, 252, 253) or a resistor (301, 302, 311, 312, 321, 322) is formed on or in the capacitor (101, 101A, 101B, 101C, 101D, 101E, 101F, 101G, 101H, 101J, 1101, 1101′, 1101″, 1101′″, 1101″″, 1101′″″).

Abstract translation: 一种布线板，包括：具有芯主表面（12）和芯反向表面（13）的板芯（11）; 一个电容器（101,101A，101B，101C，101D，101E，101F，101G，101H，101J，1101,1101'，1101“，1101”'，1101“ 具有电容器主表面（102）和电容器反面（103）的第一内电极层（141）和第二内电极层（142）交替层叠的结构的电容器（1101“'），1101” 电容器（101,101A，101B，101C，101D，101E，101F，101G，101H，101J，1101,1101），1101“，经由电介质层（105） 1101“，1101”“，1101”“”）以芯主表面（12）和电容器主表面（102）取向为的状态容纳在板芯（11）中 同一边 以及具有层间绝缘层（33,35）和导体层（42）交替层叠在芯主表面（12）和电容器主表面（102）上的结构的布线层叠部分（31），其中电感器 （101,21A，101B，101C，101D，101E，101F）上形成有电阻（251,252,253）或电阻器（301,302,311,312,321,322） ，101G，101H，101J，1101,1101'，1101“，1101”'，1101“'，1101”''）。

公开(公告)号：US20070013442A1

公开(公告)日：2007-01-18

申请号：US11452405

申请日：2006-06-14

Applicant: Dirk Wiegner ,  Thomas Merk

Inventor： Dirk Wiegner ,  Thomas Merk

IPC: H03F1/00

CPC classification number: H03F3/195 ,  H03F2200/144 ,  H03F2200/147 ,  H03F2200/451 ,  H05K1/0243 ,  H05K1/181 ,  H05K2201/10045 ,  H05K2201/10166 ,  H05K2201/10515 ,  H05K2201/1053 ,  Y02P70/611

Abstract: An amplifier, in particular for RF-applications, comprises a circuit board (2), at least one amplifier stage with at least one transistor package (8) arranged on the circuit board (2), and a feedback path (12) around the at least one transistor package (8), said feedback path (12) comprising a feedback element (15) with at least one capactive (C) element for blocking the flow of direct current through the feedback path (12) and preferably further comprising at least one inductive (L) and/or resistive element (R). In order to reduce negative effects on the performance of the amplifier due to long printed feedback lines, the feedback path (12) in an amplifier according to the invention is formed of a feedback bridge (9) comprising two feedback lines (13, 14) extending out of the plane of the circuit board (2) from two contact flags (10, 11) of the transistor package (8), and the feedback element (15) bridging over the transistor package (8) between the two feedback lines (13, 14).

Abstract translation: 特别是用于RF应用的放大器包括电路板（2），至少一个具有布置在电路板（2）上的至少一个晶体管封装（8）的放大器级，以及围绕 至少一个晶体管封装（8），所述反馈路径（12）包括具有至少一个负载（C）元件的反馈元件（15），用于阻断通过所述反馈路径（12）的直流电流，并且优选地还包括 至少一个电感（L）和/或电阻元件（R）。 为了减少由于长的印刷反馈线引起的放大器的性能的负面影响，根据本发明的放大器中的反馈路径（12）由包括两个反馈线（13,14）的反馈桥（9）形成， 从晶体管封装（8）的两个接触标记（10,11）延伸出电路板（2）的平面，并且反馈元件（15）跨接在两个反馈线之间的晶体管封装（8）上 13,14）。

公开(公告)号：US07154373B2

公开(公告)日：2006-12-26

申请号：US10506947

申请日：2002-03-25

Applicant: Eiji Kobayashi

Inventor： Eiji Kobayashi

IPC: H01C1/01

CPC classification number: H01G2/065 ,  H01C1/01 ,  H05K3/3442 ,  H05K2201/09181 ,  H05K2201/09781 ,  H05K2201/10045 ,  Y02P70/613

Abstract: A surface mounting chip network component in which a network having three or more odd number of terminals are formed on the surface of an insulating substrate and Tomb Stone Phenomenon is suppressed. Even number of network circuits are formed on the surface of the insulating substrate (2) and the same number of terminals (1) are arranged, respectively, on the opposite sides of the insulating substrate (2). Alternatively, even number of network circuits are formed on the surface of the insulating substrate (2) and the terminals (1) are arranged on the side edges of the insulating substrate (2) point-symmetrically with respect to the center of the surface of the insulating substrate (2).

Abstract translation: 在绝缘基板的表面上形成具有三个以上奇数个端子的网络的表面安装芯片网络部件被抑制。 在绝缘基板（2）的表面上形成有多个网络电路，并且在绝缘基板（2）的相对侧分别配置有相同数量的端子（1）。 或者，在绝缘基板（2）的表面上形成有多个网络电路，并且端子（1）相对于表面的中心点对称地配置在绝缘基板（2）的侧缘 绝缘基板（2）。

公开(公告)号：US20060133056A1

公开(公告)日：2006-06-22

申请号：US11014962

申请日：2004-12-20

Applicant: Aneta Wyrzykowska ,  Herman Kwong ,  Kah Soh

Inventor： Aneta Wyrzykowska ,  Herman Kwong ,  Kah Soh

IPC: H05K7/06 ,  H05K1/18

CPC classification number: H05K1/0246 ,  H01L2224/16225 ,  H05K1/023 ,  H05K1/141 ,  H05K1/16 ,  H05K1/162 ,  H05K1/165 ,  H05K1/167 ,  H05K1/184 ,  H05K3/4046 ,  H05K3/4053 ,  H05K2201/0187 ,  H05K2201/10045 ,  H05K2201/10545 ,  H05K2201/10636 ,  H05K2201/10734 ,  Y02P70/611

Abstract: A technique for enhancing circuit density and performance is disclosed. In one particular exemplary embodiment, the technique may be realized as a method for enhancing circuit density and performance of a microelectronic module. The method may comprise forming a discrete package, wherein the discrete package comprises one or more passive devices that are desirable for the performance of the microelectronic module. The method may also comprise coupling the discrete package to the microelectronic module.

公开(公告)号：US20050285713A1

公开(公告)日：2005-12-29

申请号：US10533035

申请日：2003-10-28

Applicant: Takahiro Kuriyama

Inventor： Takahiro Kuriyama

IPC: H01C1/16 ,  H01C13/02 ,  H05K3/34 ,  H01C1/02

CPC classification number: H05K3/3442 ,  H01C1/16 ,  H01C13/02 ,  H05K2201/09172 ,  H05K2201/10045 ,  Y02P70/613

Abstract: A fixed resistor network has an insulating substrate, a plurality of film resistors arranged on a top surface of the insulating substrate, terminal electrodes formed for the film resistors on each lengthwise sidewall of the insulating substrate at a given pitch along the sidewall, and recesses provided between the terminal electrodes. The occurrence of solder bridges between the terminal electrodes during solder mounting and the occurrence of chipping in the terminal-electrode-forming areas between the recesses on the lengthwise sidewall are both reduced by making the width of the recesses along the lengthwise sidewall either 0.44 to 0.48 times or 0.525 to 0.625 times the pitch.

Abstract translation: 固定电阻网络具有绝缘基板，布置在绝缘基板的顶表面上的多个薄膜电阻器，沿着侧壁以给定的间距为绝缘基板的每个纵向侧壁上的薄膜电阻器形成的端子电极和设置的凹部 在端子电极之间。 在焊接安装期间在端子电极之间出现焊接桥，并且在纵向侧壁上的凹部之间的端子电极形成区域中发生切屑的情况都通过使沿着纵向侧壁的凹部的宽度为0.44至0.48 次或0.525到0.625倍。

公开(公告)号：US20050035450A1

公开(公告)日：2005-02-17

申请号：US10640073

申请日：2003-08-13

Applicant: David Poole ,  Terry Bloom ,  Richard Cooper

Inventor： David Poole ,  Terry Bloom ,  Richard Cooper

IPC: H01C1/14 ,  H05K1/02 ,  H05K1/14 ,  H05K1/16 ,  H05K3/28 ,  H05K3/34 ,  H01L23/48

CPC classification number: H05K1/0268 ,  H01C1/14 ,  H05K1/141 ,  H05K1/167 ,  H05K3/28 ,  H05K3/3436 ,  H05K2201/10045

Abstract: A ball grid array package that can be readily tested before or after mounting to a printed circuit board. The ball grid array includes a substrate having a top surface and a bottom surface. Several conductive pads are located on the top surface. Several passive circuit elements are located on the top surface between the conductive pads. An insulative coating is placed on top of the passive circuit elements and the substrate. The insulative coating has openings over the conductive pads. The openings are adapted to be accessible by an electrical probe. Conductive vias extend through the substrate between the top and bottom surfaces. The vias electrically connect with the conductive pad on the top surface. Several conductive balls are located on the bottom surface. Each conductive ball is electrically connected to one of the vias.

公开(公告)号：US06727782B2

公开(公告)日：2004-04-27

申请号：US10192155

申请日：2002-07-11

Applicant: Tomohiro Sasaki ,  Takahiro Azuma ,  Shigekatsu Yamamoto

Inventor： Tomohiro Sasaki ,  Takahiro Azuma ,  Shigekatsu Yamamoto

IPC: H03H701

CPC classification number: H03H7/0115 ,  H03H2001/0085 ,  H05K1/0243 ,  H05K3/3442 ,  H05K2201/09381 ,  H05K2201/09954 ,  H05K2201/10045 ,  Y02P70/613

Abstract: A multilayered LC composite component includes a main body having a pair of side surfaces, a pair of end surfaces, and an upper surface and a lower surface. Ground-side terminal electrodes are disposed at the center of the side surfaces and hot-side terminal electrodes are disposed along edges of the side surfaces. Each of the hot-side terminal electrodes includes an end surface extended portion extending to each of the end surfaces. The end-surface extended portion is arranged so that at least the approximate center of each of the end surfaces is exposed.

Abstract translation: 多层LC复合部件包括具有一对侧面，一对端面以及上表面和下表面的主体。 接地侧端子电极设置在侧面的中心，热侧端子电极沿着侧面的边缘设置。 每个热侧端子电极包括延伸到每个端面的端面延伸部分。 端面延伸部分被布置成使得至少每个端面的大致中心被露出。

公开(公告)号：US06704209B2

公开(公告)日：2004-03-09

申请号：US09892746

申请日：2001-06-28

Applicant: Hiroshi Yamauchi ,  Minoru Yamamoto

Inventor： Hiroshi Yamauchi ,  Minoru Yamamoto

IPC: H05K116

CPC classification number: H05K3/3442 ,  H01C1/012 ,  H01G4/40 ,  H05K2201/10045 ,  H05K2201/10537 ,  Y02P70/613

Abstract: Three or more, or two or more types of electronic components are formed on one substrate, and these electronic components form an aggregated planar surface on a surface of the substrate.

Abstract translation: 在一个基板上形成三种以上或两种以上的电子部件，这些电子部件在基板的表面上形成凝集的平面。