公开(公告)号：US20090162978A1

公开(公告)日：2009-06-25

申请号：US12395506

申请日：2009-02-27

申请人： Vladislav Vashchenko ,  Peter J. Hopper

发明人： Vladislav Vashchenko ,  Peter J. Hopper

IPC分类号： H01L21/332

CPC分类号： H01L27/0259

摘要： A diode for alternating current (DIAC) electrostatic discharge (ESD) protection circuit is formed in a silicon germanium (SiGe) hetrojunction bipolar transistor (HBT) process that utilizes a very thin collector region. ESD protection for a pair of to-be-protected pads is provided by utilizing the base structures and the emitter structures of the SiGe transistors.

摘要翻译： 用于交流（DIAC）静电放电（ESD）保护电路的二极管形成在利用非常薄的集电极区域的硅锗（SiGe）合金双极晶体管（HBT）工艺中。 通过利用SiGe晶体管的基极结构和发射极结构，提供一对待保护焊盘的ESD保护。

公开(公告)号：US07547585B2

公开(公告)日：2009-06-16

申请号：US11085635

申请日：2005-03-21

申请人： Milton J Boden

发明人： Milton J Boden

IPC分类号： H01L21/332

CPC分类号： H01L29/7802 ,  H01L29/0847 ,  H01L29/0878 ,  H01L29/66712

摘要： A P channel vertical conduction Rad Hard MOSFET has a plurality of closely spaced base strips which have respective sources to form invertible surface channels with the opposite sides of each of the stripes. A non-DMOS late gate oxide and overlying conductive polysilicon gate are formed after the source and base regions have been diffused. The base stripes are spaced by about 0.6 microns, and the polysilicon gate stripes are about 3.2 microns wide. A P type enhancement region is implanted through spaced narrow windows early in the process and are located in the JFET common conduction region which is later formed by and between the spaced base stripes. The device is a high voltage (greater than 25 volts) P channel device with very low gate capacitance and very low on resistance.

摘要翻译： P沟道垂直导电Rad Hard MOSFET具有多个紧密间隔的基带，其具有各自的源以与每个条纹的相对侧形成可逆表面通道。 在源极和基极区域扩散之后形成非DMOS后栅极氧化物和上覆导电多晶硅栅极。 基条间隔约0.6微米，多晶硅栅极条宽约为3.2微米。 P型增强区域在工艺早期通过间隔窄的窗口植入，并且位于JFET共同导电区域中，后者由间隔开的基底条纹之间和之间形成。 该器件是具有非常低栅极电容和非常低导通电阻的高电压（大于25伏特）P沟道器件。

公开(公告)号：US07541242B2

公开(公告)日：2009-06-02

申请号：US11346413

申请日：2006-02-02

申请人： Kirk D. Prall ,  Leonard Forbes

发明人： Kirk D. Prall ,  Leonard Forbes

IPC分类号： H01L21/332

CPC分类号： H01L29/7926 ,  G11C11/5692 ,  G11C16/0466 ,  G11C16/0475 ,  H01L27/11556 ,  H01L27/11582 ,  H01L29/7889 ,  H01L29/7923

摘要： An array of memory cells configured to store at least one bit per one F2 includes substantially vertical structures providing an electronic memory function spaced apart a distance equal to one half of a minimum pitch of the array. The structures providing the electronic memory function are configured to store more than one bit per gate. The array also includes electrical contacts to the memory cells including the substantially vertical structures. The cells can be programmed to have one of a number of charge levels trapped in the gate insulator adjacent to the first source/drain region such that the channel region has a first voltage threshold region (Vt1) and a second voltage threshold region (Vt2) and such that the programmed cell operates at reduced drain source current.

摘要翻译： 配置为存储每个F2的至少一个位的存储器单元的阵列包括基本上垂直的结构，提供间隔距离等于阵列的最小间距的一半的距离的电子存储器功能。 提供电子存储器功能的结构被配置为存储每个门多于一个位。 阵列还包括到存储器单元的电接触，包括基本垂直的结构。 电池可以被编程为具有与栅极绝缘体相邻的多个电荷水平中的一个，其邻近于第一源极/漏极区域，使得沟道区域具有第一电压阈值区域（Vt1）和第二电压阈值区域（Vt2） 并且使得编程单元以降低的漏极源电流工作。

公开(公告)号：US07528016B2

公开(公告)日：2009-05-05

申请号：US11519818

申请日：2006-09-13

申请人： Yasushi Yamazaki

发明人： Yasushi Yamazaki

IPC分类号： H01L21/332

CPC分类号： H01L21/823481 ,  H01L27/10876 ,  H01L29/66621

摘要： In a method of manufacturing a semiconductor device, a recess is formed in a semiconductor substrate. A gate insulating film is formed on a surface of the semiconductor substrate and a surface of the recess; and a gate electrode film is deposited on the gate insulating film to fill the recess. Then, a gate electrode is formed by etching the gate electrode film by using a predetermined mask, and ion implantation into the semiconductor substrate is carried out to form diffusion layers extending from the recess, before the forming a gate electrode at least.

摘要翻译： 在制造半导体器件的方法中，在半导体衬底中形成凹部。 在半导体衬底的表面和凹部的表面上形成栅极绝缘膜; 并且在栅极绝缘膜上沉积栅极电极膜以填充凹部。 然后，通过使用预定的掩模蚀刻栅极电极膜来形成栅电极，并且至少在形成栅电极之前，进行到半导体衬底的离子注入以形成从凹部延伸的扩散层。

公开(公告)号：US07498619B2

公开(公告)日：2009-03-03

申请号：US11362435

申请日：2006-02-23

申请人： Mario G. Saggio ,  Ferruccio Frisina

发明人： Mario G. Saggio ,  Ferruccio Frisina

IPC分类号： H01L21/332

CPC分类号： H01L29/66712 ,  H01L29/0634 ,  H01L29/0847 ,  H01L29/1095

摘要： A power electronic device is integrated on a semiconductor substrate of a first type of conductivity. The device includes a plurality of elemental units, and each elemental unit includes a body region of a second type of conductivity which is realized on a semiconductor layer of the first type of conductivity formed on the semiconductor substrate, and a column region of the first type of conductivity which is realized in said semiconductor layer below the body region. The semiconductor layer includes multiple semiconductor layers which overlap each other. The resistivity of each layer is different from that of the other layers. The column region includes a plurality of doped sub-regions, each realized in one of the semiconductor layers. The amount of charge of each doped sub-region balances the amount of charge of the corresponding semiconductor layer in which each doped sub-region is realized.

摘要翻译： 功率电子器件集成在第一导电类型的半导体衬底上。 该器件包括多个元件单元，并且每个元件单元包括在形成于半导体衬底上的第一类型导电体的半导体层上实现的第二导电类型的主体区域和第一类型的列区域 的导电性，其在身体区域下方的所述半导体层中实现。 半导体层包括彼此重叠的多个半导体层。 每层的电阻率与其他层的电阻率不同。 列区域包括多个掺杂的子区域，每个都在半导体层之一中实现。 每个掺杂子区域的电荷量平衡了实现每个掺杂子区域的相应半导体层的电荷量。

公开(公告)号：US20090050932A1

公开(公告)日：2009-02-26

申请号：US11817683

申请日：2006-02-28

申请人： Hong-fei Lu ,  Shinichi Jimbo

发明人： Hong-fei Lu ,  Shinichi Jimbo

IPC分类号： H01L29/739 ,  H01L21/332

CPC分类号： H01L29/7802 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/0623 ,  H01L29/0653 ,  H01L29/0878 ,  H01L29/42368 ,  H01L29/456 ,  H01L29/66333 ,  H01L29/66348 ,  H01L29/7395 ,  H01L29/7397 ,  H01L29/7813

摘要： To provide a semiconductor device that exhibits a high breakdown voltage, excellent thermal properties, a high latch-up withstanding capability and low on-resistance. The semiconductor device according to the invention, which includes a buried insulator region 5 disposed between an n−-type drift layer 3 and a first n-type region 7 above n−-type drift layer 3, facilitates limiting the emitter hole current, preventing latch-up from occurring, raising neither on-resistance nor on-voltage. The semiconductor device according to the invention, which includes a p-type region 4 disposed between the buried insulator region 5 and n−-type drift layer 3, facilitates depleting n−-type drift layer 3 in the OFF-state of the device. The semiconductor device according to the invention, which includes a second n-type region 6 disposed between the first n-type region 7 and the n−-type drift layer 3, facilitates dissipating the heat caused in the channel region or in the first n-type region 7 to a p+-type collector layer 1a, which is a semiconductor substrate, via the second n-type region 6, n−-type drift layer 3 and an n-type buffer layer 2.

摘要翻译： 提供具有高击穿电压，优异的热性能，高闩锁耐受能力和低导通电阻的半导体器件。 根据本发明的半导体器件，其包括设置在n型漂移层3和n型漂移层3上方的第一n型区域7之间的掩埋绝缘体区域5，有助于限制发射极空穴电流，防止 产生闩锁，不会产生导通电阻或导通电压。 根据本发明的半导体器件，其包括设置在掩埋绝缘体区域5和n型漂移层3之间的p型区域4，有助于在器件的截止状态下耗尽n型漂移层3。 根据本发明的半导体器件，其包括设置在第一n型区域7和n型漂移层3之间的第二n型区域6，有助于散发在沟道区域或第一n型区域中产生的热量 通过第二n型区域6，n型漂移层3和n型缓冲层2，作为半导体衬底的p +型集电极层1a至n +型集电极层1a。

公开(公告)号：US07494854B2

公开(公告)日：2009-02-24

申请号：US11768814

申请日：2007-06-26

申请人： Ming-Dou Ker ,  Che-Hao Chuang

发明人： Ming-Dou Ker ,  Che-Hao Chuang

IPC分类号： H01L29/74 ,  H01L21/332

CPC分类号： H01L27/0266

摘要： A semiconductor device suitable for applications in an electrostatic discharge (ESD) protection circuit, including a semiconductor substrate, a first well formed in the substrate, a second well formed in the substrate, and a first doped region formed in the second well, wherein the first well, the second well, and the first doped region collectively form a parasitic bipolar junction transistor (BJT), and wherein the first well is the collector of the BJT, the second well is the base of the BJT, and the first doped region is the emitter of the BJT.

公开(公告)号：US07491586B2

公开(公告)日：2009-02-17

申请号：US11159514

申请日：2005-06-22

申请人： Andrew E Horch ,  Hyun-Jin Cho ,  Farid Nemati ,  Scott Robins ,  Rajesh N. Gupta ,  Kevin J. Yang

发明人： Andrew E Horch ,  Hyun-Jin Cho ,  Farid Nemati ,  Scott Robins ,  Rajesh N. Gupta ,  Kevin J. Yang

IPC分类号： H01L21/332 ,  H01L21/04 ,  H01L21/425

CPC分类号： G11C11/39 ,  H01L27/0817 ,  H01L29/7436 ,  H01L29/7455 ,  H01L29/749

摘要： A method of fabricating a thyristor-based memory may include forming different opposite conductivity-type regions in silicon for defining a thyristor and an access device in series relationship. An activation anneal may activate dopants previously implanted for the different regions. A damaging implant of germanium or xenon or argon may be directed into select regions of the silicon including at least one p-n junction region for the access device and the thyristor. A re-crystallization anneal may then be performed to re-crystallize at least some of the damaged lattice structure resulting from the damaging implant. The re-crystallization anneal may use a temperature less than that of the previous activation anneal.

摘要翻译： 制造基于晶闸管的存储器的方法可以包括在硅中形成用于限定可控硅和串联连接的存取装置的不同的相反导电型区域。 激活退火可以激活先前为不同区域植入的掺杂剂。 可以将锗或氙或氩的有害植入物引导到硅的选择区域中，包括用于进入装置和晶闸管的至少一个p-n结区域。 然后可以进行重结晶退火，以重新结晶由损伤性植入物引起的至少一些损伤的晶格结构。 再结晶退火可以使用比先前激活退火的温度低的温度。

公开(公告)号：US20080303056A1

公开(公告)日：2008-12-11

申请号：US11758859

申请日：2007-06-06

申请人： Terence G. Ward ,  Edward P. Yankoski

发明人： Terence G. Ward ,  Edward P. Yankoski

IPC分类号： H01L29/74 ,  H01L21/332

CPC分类号： H01L24/40 ,  H01L24/37 ,  H01L25/072 ,  H01L2224/37011 ,  H01L2224/40091 ,  H01L2224/40225 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/00

摘要： A semiconductor subassembly is provided for use in a switching module of an inverter circuit for a high power, alternating current motor application. The semiconductor subassembly includes a wafer having first and second opposed metallized faces; a semiconductor switching device electrically coupled to the first metallized face of the wafer and having at least one electrode region; and an interconnect bonded to the semiconductor switching device. The interconnect includes a first metal layer bonded to the at least one electrode region of the semiconductor switching device, a ceramic layer bonded to the first metal layer, the ceramic layer defining a via for accessing the first metal layer, a second metal layer bonded to the ceramic layer, and a conducting substance disposed in the via of the ceramic layer to electrically couple the first metal layer to the second metal layer.

摘要翻译： 提供了一种用于大功率，交流电动机应用的逆变器电路的开关模块中的半导体子组件。 半导体子组件包括具有第一和第二相对的金属化面的晶片; 电耦合到所述晶片的所述第一金属化面并且具有至少一个电极区域的半导体开关器件; 以及连接到半导体开关器件的互连。 互连包括结合到半导体开关器件的至少一个电极区域的第一金属层，接合到第一金属层的陶瓷层，限定用于接触第一金属层的通孔的陶瓷层，接合到第一金属层的第二金属层 陶瓷层和设置在陶瓷层的通孔中的导电物质，以将第一金属层电耦合到第二金属层。

公开(公告)号：US20080258690A1

公开(公告)日：2008-10-23

申请号：US12157954

申请日：2008-06-13

申请人： Akihiro Odagawa ,  Yasunari Sugita ,  Hideaki Adachi ,  Masahiro Deguchi

发明人： Akihiro Odagawa ,  Yasunari Sugita ,  Hideaki Adachi ,  Masahiro Deguchi

IPC分类号： H02J7/04 ,  H01L21/332

CPC分类号： H01L37/00 ,  F25B2321/003 ,  F25B2400/15

摘要： The present invention provides a thermal switching element that has a quite different configuration from that of a conventional technique and can control heat transfer by the application of energy, and a method for manufacturing the thermal switching element. The thermal switching element includes a first electrode, a second electrode, and a transition body arranged between the first electrode and the second electrode. The transition body includes a material that causes an electronic phase transition by application of energy. The thermal conductivity between the first electrode and the second electrode is changed by the application of energy to the transition body.

摘要翻译： 本发明提供一种具有与常规技术相当不同的构造并且可以通过施加能量来控制热传递的热开关元件，以及用于制造热开关元件的方法。 热开关元件包括第一电极，第二电极和布置在第一电极和第二电极之间的过渡体。 过渡体包括通过施加能量引起电子相变的材料。 第一电极和第二电极之间的热导率通过向能量转移体施加能量来改变。