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3950 条记录 (耗时 0.039 秒)

    TRANSMITTER FOR TRANSMITTING MULTI-BIT DATA
    62.
    发明申请
    TRANSMITTER FOR TRANSMITTING MULTI-BIT DATA 有权

    公开(公告)号：US20210367598A1

    公开(公告)日：2021-11-25

    申请号：US17164627

    申请日：2021-02-01

    申请人： SK hynix Inc. ,  Seoul National University R&DB Foundation

    发明人： Changho HYUN ,  Suhwan KIM

    IPC分类号： H03K19/017 ,  H03K19/17728 ,  H03K19/0185 ,  H03K19/09 ,  H03K19/173

    摘要： A transmitter includes a driving circuitry configured to drive a channel coupled to an output node by controlling an output impedance of a pull-up path, an output impedance of a pull-down path, or both, according to one or more multi-bit data signals, a pull-up control signal, and a pull-down control signal; a driving control circuit configured to generate the pull-up control signal and the pull-down control signal according to one or more calibration signals and the multi-bit data signals or according to the calibration signals and one or more duplicate multi-bit data signals, the duplicate multi-bit data signals duplicating the multi-bit data signals; and a look-up table storing values of the calibration signals.

    Semiconductor field programmable device
    63.
    发明授权
    Semiconductor field programmable device 有权

    公开(公告)号：US11184005B2

    公开(公告)日：2021-11-23

    申请号：US17037522

    申请日：2020-09-29

    申请人： Ben Sheen

    发明人： Ben Sheen

    IPC分类号： H03K19/173 ,  H03K19/17736 ,  H03K19/1776

    摘要： A field programmable device or software-defined hardware can change its functions by using software codes to alter the routing path of interconnect signal lines or the electrical properties of fundamental building elements. The field programmable device includes I/O interface blocks and signal processing blocks comprising analog signal processing units, digital signal processing units, memory units, clock units, and other supporting functional units which are electrically connected by user programmable interconnect signal lines. The analog signal processing functions can be altered by changing the electrical properties of fundamental building elements as well as the programmable signal lines after the device is manufactured.

    Reversible logic circuit and operation method thereof
    64.
    发明授权
    Reversible logic circuit and operation method thereof 有权

    公开(公告)号：US11171650B2

    公开(公告)日：2021-11-09

    申请号：US16965602

    申请日：2019-07-16

    申请人： HUAZHONG UNIVERSITY OF SCIENCE AND TECHNOLOGY

    发明人： Yi Li ,  Long Cheng ,  Xiangshui Miao

    IPC分类号： H03K19/177 ,  H03K19/173

    摘要： A reversible logic circuit and an operation method thereof are provided. The logic circuit includes resistive switching cells, word lines, and bit lines. The word lines and the bit lines are perpendicular to each other. The anode of a resistive switching cell is connected to the word line as a first input terminal to apply logic operating voltage or be grounded. The cathode of a resistive switching cell is connected to the bit line as a second input terminal to apply logic operating voltage or be grounded. When performing reversible logic operation, four levels of resistance states of the resistive switching cell are used as logic outputs to implement single-input NOT and dual-input C-NOT reversible logic functions.

    DIRECT MEMORY ACCESS USING JTAG CELL ADDRESSING
    65.
    发明申请
    DIRECT MEMORY ACCESS USING JTAG CELL ADDRESSING 有权

    公开(公告)号：US20210335438A1

    公开(公告)日：2021-10-28

    申请号：US16624665

    申请日：2019-05-31

    申请人： Micron Technology, Inc.

    发明人： Alberto Troia ,  Antonino Mondello

    IPC分类号： G11C29/32 ,  G11C29/42 ,  G11C7/06 ,  G11C7/10 ,  H03K19/173

    摘要： The present disclosure relates to a Flash memory component having a structurally independent structure and coupled to a System-on-Chip through a plurality of interconnection pads, comprising: a memory array including a plurality of independently addressable sub arrays; sense amplifiers coupled to corresponding outputs of said sub arrays and coupled to a communication channel of said System-on-Chip; a scan-chain comprising modified JTAG cells coupled in parallel between the output of the sense amplifiers and said communication channel to allow performing read operations in a Direct Memory Access. A method for retrieving data from the memory component is also disclosed.

    JTAG BASED ARCHITECTURE ALLOWING MULTI-CORE OPERATION
    66.
    发明申请
    JTAG BASED ARCHITECTURE ALLOWING MULTI-CORE OPERATION 有权

    公开(公告)号：US20210335435A1

    公开(公告)日：2021-10-28

    申请号：US16625479

    申请日：2019-05-31

    申请人： Micron Technology, Inc.

    发明人： Alberto Troia ,  Antonino Mondello

    IPC分类号： G11C29/16 ,  G11C29/32 ,  G11C7/06 ,  G11C7/10 ,  H03K19/173

    摘要： The present disclosure relates to an apparatus comprising:
    a memory component having an independent structure and including at least an array of memory cells with associated decoding and sensing circuitry and a memory controller;
    a host device including multiple cores and coupled to the memory component through at least a communication channel for each corresponding core;
    a control and JTAG interface in said at least an array of memory cells;
    at least an additional register in said control and JTAG interface for handing data, addresses and control signals provided by the host device and to be delivered to said decoding circuitry and to said controller to perform modify operations.

    Logic Configuration Techniques
    68.
    发明申请
    Logic Configuration Techniques 有权

    公开(公告)号：US20210305985A1

    公开(公告)日：2021-09-30

    申请号：US16991018

    申请日：2020-08-12

    申请人： Arm Limited

    发明人： Anil Kumar Baratam

    IPC分类号： H03K19/094 ,  H03K19/0944 ,  H03K19/17736 ,  H03K19/173 ,  H03K3/0233

    摘要： Various implementations described herein are directed to a device having logic circuitry with multiple inversion stages. One or more of the multiple inversion stages may be configured to operate as first inversion logic with a first number of transistors. One or more of the multiple inversion stages may be configured to operate as second inversion logic with a second number of transistors that is greater than the first number of transistors.

    Semiconductor integrated circuit
    70.
    再颁专利
    Semiconductor integrated circuit 有权

    公开(公告)号：USRE48694E1

    公开(公告)日：2021-08-17

    申请号：US13687996

    申请日：2012-11-28

    申请人： Sony Corporation

    发明人： Hiromi Ogata

    IPC分类号： H03K19/173 ,  H01L27/02 ,  H01L27/118 ,  H03K19/00 ,  H01L23/528

    摘要： A semiconductor integrated circuit able to reduce a load of layout design when arranging switches in a power lines for preventing leakage current and able to reduce the influence of a voltage drop occurring in the switches on a signal delay, wherein a plurality of groups of power lines are arranged in stripe shapes, power is supplied to circuit cells by a plurality of groups of branch lines branching from the groups of power lines, power switch cells arranged in the groups of branch lines turn on or off the supply of power to the circuit cells, the power switch cells are arranged dispersed in the area of arrangement of the circuit cells, and the supply of power by the power switch cells is finely controlled for every relatively small number of circuit cells.