公开(公告)号：US12051691B2

公开(公告)日：2024-07-30

申请号：US17020507

申请日：2020-09-14

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

发明人： Po-Lin Peng ,  Han-Jen Yang ,  Jam-Wem Lee ,  Li-Wei Chu

IPC分类号： H01L27/02 ,  H01L23/528 ,  H01L27/07 ,  H01L29/06 ,  H01L29/10 ,  H01L29/861

CPC分类号： H01L27/0277 ,  H01L23/5286 ,  H01L27/0722 ,  H01L29/0649 ,  H01L29/1083 ,  H01L29/861

摘要： An electrostatic discharge (ESD) protection device having a source region coupled to a first electrical node, a first drain region coupled to a second electrical node different from the first electrical node, and an extended drain region between the source region and the first drain region. The extended drain region includes a number N of electrically floating doped regions and a number M of gate regions coupled to the second electrical node, where N and M are integers greater than 1 and N is equal to M. Each electrically floating doped region of the N number of floating doped regions alternates with each gate region of the M number of gate regions.

公开(公告)号：US20240251563A1

公开(公告)日：2024-07-25

申请号：US18623956

申请日：2024-04-01

申请人： Micron Technology, Inc.

发明人： Kamal M. Karda ,  Eric S. Carman ,  Karthik Sarpatwari ,  Durai Vishak Nirmal Ramaswamy ,  Richard E. Fackenthal ,  Haitao Liu

IPC分类号： H10B43/50 ,  H01L29/10 ,  H01L29/423

CPC分类号： H10B43/50 ,  H01L29/1062 ,  H01L29/42396

摘要： Some embodiments include apparatuses and methods forming the apparatuses. One of the apparatuses includes a first transistor including a first channel region, and a charge storage structure separated from the first channel region; a second transistor including a second channel region formed over the charge storage structure; and a data line formed over and contacting the first channel region and the second channel region, the data line including a portion adjacent the first channel region and separated from the first channel region by a dielectric material.

公开(公告)号：US20240250172A1

公开(公告)日：2024-07-25

申请号：US18627266

申请日：2024-04-04

申请人： Acorn Semi, LLC

发明人： Paul A. Clifton ,  R. Stockton Gaines

IPC分类号： H01L29/78 ,  H01L21/02 ,  H01L21/762 ,  H01L21/8234 ,  H01L21/8238 ,  H01L21/84 ,  H01L27/12 ,  H01L29/06 ,  H01L29/10 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66 ,  H01L29/786

CPC分类号： H01L29/7849 ,  H01L21/0245 ,  H01L21/02532 ,  H01L21/7624 ,  H01L21/76251 ,  H01L21/76254 ,  H01L21/76283 ,  H01L21/823412 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/0649 ,  H01L29/105 ,  H01L29/1054 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66477 ,  H01L29/66568 ,  H01L29/66742 ,  H01L29/7838 ,  H01L29/7846 ,  H01L29/78603 ,  H01L21/823807

摘要： An SOI wafer contains a compressively stressed buried insulator structure. In one example, the stressed buried insulator (BOX) may be formed on a host wafer by forming silicon oxide, silicon nitride and silicon oxide layers so that the silicon nitride layer is compressively stressed. Wafer bonding provides the surface silicon layer over the stressed insulator layer. Preferred implementations of the invention form MOS transistors by etching isolation trenches into a preferred SOI substrate having a stressed BOX structure to define transistor active areas on the surface of the SOI substrate. Most preferably the trenches are formed deep enough to penetrate through the stressed BOX structure and some distance into the underlying silicon portion of the substrate. The overlying silicon active regions will have tensile stress induced due to elastic edge relaxation.

公开(公告)号：US20240250170A1

公开(公告)日：2024-07-25

申请号：US18625798

申请日：2024-04-03

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD. ,  TSMC China Company Limited

发明人： Lian-Jie LI ,  Yan-Bin LU ,  Feng HAN ,  Shuai ZHANG

IPC分类号： H01L29/78 ,  H01L21/265 ,  H01L21/266 ,  H01L29/06 ,  H01L29/10 ,  H01L29/66

CPC分类号： H01L29/7835 ,  H01L21/26513 ,  H01L21/26586 ,  H01L21/266 ,  H01L29/0653 ,  H01L29/1095 ,  H01L29/6659 ,  H01L29/66681 ,  H01L29/7816

摘要： A semiconductor device includes a gate structure, a drift region, a source region, a drain region, a first doped region, and a second doped region. The gate structure is over a semiconductor substrate. The drift region is in the semiconductor substrate and laterally extends past a first side of the gate structure. The source region is in the semiconductor substrate and adjacent a second side of the gate structure opposite the first side. The drain region is in the drift region. The first doped region is in the drift region and between the drain region and the gate structure. The second doped region is within the drift region. The second doped region forms a P-N junction with the first doped region at a bottom surface of the first doped region.

公开(公告)号：US20240250167A1

公开(公告)日：2024-07-25

申请号：US18625430

申请日：2024-04-03

申请人： FUJI ELECTRIC CO., LTD.

发明人： Keiji OKUMURA

IPC分类号： H01L29/78 ,  H01L21/04 ,  H01L29/08 ,  H01L29/10 ,  H01L29/16 ,  H01L29/36 ,  H01L29/423 ,  H01L29/66

CPC分类号： H01L29/7813 ,  H01L21/046 ,  H01L29/086 ,  H01L29/0865 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/4236 ,  H01L29/66068 ,  H01L29/7811 ,  H01L29/36

摘要： A semiconductor device includes a current spreading region of the first conductivity type provided on a drift layer and having a higher impurity density than the drift layer; a base region of a second conductivity type provided on the current spreading region; a base contact region of the second conductivity type provided in a top part of the base region and having a higher impurity density than the base region; and an electrode contact region of the first conductivity type provided in a top part of the base region that is laterally in contact with the base contact region, the electrode contact region having a higher impurity density than the drift layer, wherein a density of a second conductivity type impurity element in the base contact region is at least two times as much as a density of a first conductivity type impurity element in the electrode contact region.

公开(公告)号：US20240250125A1

公开(公告)日：2024-07-25

申请号：US18436052

申请日：2024-02-08

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Chih-Ching WANG ,  Wei-Yang LEE ,  Ming-Chang WEN ,  Jo-Tzu HUNG ,  Wen-Hsing HSIEH ,  Kuan-Lun CHENG

IPC分类号： H01L29/10 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78

CPC分类号： H01L29/1033 ,  H01L29/4238 ,  H01L29/66818 ,  H01L29/785 ,  H01L2029/7858

摘要： Embodiments of the present disclosure provide a semiconductor device structure including a first channel layer formed of a first material, wherein the first channel layer has a first width, a second channel layer formed of a second material different from the first material, wherein the second channel layer has a second width less than the first width, and the second channel layer is in contact with a first surface of the first channel layer. The structure also includes a third channel layer formed of the second material, wherein the third channel layer has a third width less than the second width, and the third channel layer is in contact with a second surface of the first channel layer. The structure also includes a gate dielectric layer conformally disposed on the first channel layer, the second channel layer, and the third channel layer, and a gate electrode layer disposed on the gate dielectric layer.

公开(公告)号：US12046671B2

公开(公告)日：2024-07-23

申请号：US17569527

申请日：2022-01-06

申请人： UNITED MICROELECTRONICS CORP.

发明人： Che-Hua Chang ,  Shin-Hung Li ,  Tsung-Yu Yang ,  Ruei-Jhe Tsao

IPC分类号： H01L29/78 ,  H01L29/10 ,  H01L29/40 ,  H01L29/423 ,  H01L29/66

CPC分类号： H01L29/7825 ,  H01L29/1095 ,  H01L29/401 ,  H01L29/42368 ,  H01L29/66704

摘要： A semiconductor device includes a semiconductor substrate, a trench, and a gate structure. The trench is disposed in the semiconductor substrate. The gate structure is disposed on the semiconductor substrate. The gate structure includes a gate electrode, a first gate oxide layer, and a second gate oxide layer. A first portion of the gate electrode is disposed in the trench, and a second portion of the gate electrode is disposed outside the trench. The first gate oxide layer is disposed between the gate electrode and the semiconductor substrate. At least a portion of the first gate oxide layer is disposed in the trench. The second gate oxide layer is disposed between the second portion of the gate electrode and the semiconductor substrate in a vertical direction. A thickness of the second gate oxide layer is greater than a thickness of the first gate oxide layer.

公开(公告)号：US12046632B2

公开(公告)日：2024-07-23

申请号：US18182893

申请日：2023-03-13

申请人： Samsung Electronics Co., Ltd.

发明人： Haejun Yu ,  Kyungin Choi ,  Seung Hun Lee

IPC分类号： H01L29/06 ,  B82Y10/00 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/08 ,  H01L29/10 ,  H01L29/161 ,  H01L29/165 ,  H01L29/417 ,  H01L29/423 ,  H01L29/49 ,  H01L29/66 ,  H01L29/775 ,  H01L29/78 ,  H01L29/786

CPC分类号： H01L29/0653 ,  H01L29/42392 ,  H01L29/4991 ,  H01L29/66553 ,  H01L27/092

摘要： A semiconductor device includes an active pattern on a substrate, a source/drain pattern on the active pattern, a channel pattern connected to the source/drain pattern, the channel pattern including semiconductor patterns stacked and spaced apart from each other, a gate electrode extending across the channel pattern, and inner spacers between the gate electrode and the source/drain pattern. The semiconductor patterns include stacked first and second semiconductor patterns. The gate electrode includes first and second portions, which are sequentially stacked between the substrate and the first and second semiconductor patterns, respectively. The inner spacers include first and second air gaps, between the first and second portions of the gate electrode and the source/drain pattern. The largest width of the first air gap is larger than that of the second air gap.

公开(公告)号：US12046517B2

公开(公告)日：2024-07-23

申请号：US17495696

申请日：2021-10-06

申请人： Tahoe Research, Ltd.

发明人： Glenn A. Glass ,  Daniel B. Aubertine ,  Anand S. Murthy ,  Gaurav Thareja ,  Tahir Ghani

IPC分类号： H01L21/8238 ,  H01L21/8258 ,  H01L29/10

CPC分类号： H01L21/823807 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/8258 ,  H01L29/1054

摘要： Techniques are disclosed for customization of fin-based transistor devices to provide a diverse range of channel configurations and/or material systems within the same integrated circuit die. In accordance with one example embodiment, sacrificial fins are removed and replaced with custom semiconductor material of arbitrary composition and strain suitable for a given application. In one such case, each of a first set of the sacrificial fins is recessed or otherwise removed and replaced with a p-type material, and each of a second set of the sacrificial fins is recessed or otherwise removed and replaced with an n-type material. The p-type material can be completely independent of the process for the n-type material, and vice-versa. Numerous other circuit configurations and device variations are enabled using the techniques provided herein.

公开(公告)号：US20240243122A1

公开(公告)日：2024-07-18

申请号：US18416702

申请日：2024-01-18

申请人： STMICROELECTRONICS S.R.L.

发明人： Mario Giuseppe SAGGIO ,  Simone RASCUNÁ

IPC分类号： H01L27/06 ,  H01L21/04 ,  H01L29/06 ,  H01L29/08 ,  H01L29/10 ,  H01L29/16 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78 ,  H01L29/872

CPC分类号： H01L27/0629 ,  H01L21/046 ,  H01L29/0619 ,  H01L29/0696 ,  H01L29/0847 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/4238 ,  H01L29/66068 ,  H01L29/7806 ,  H01L29/872

摘要： An integrated MOSFET device is formed in a body of silicon carbide and with a first type of conductivity. The body accommodates a first body region, with a second type of conductivity; a JFET region adjacent to the first body region; a first source region, with the first type of conductivity, extending into the interior of the first body region; an implanted structure, with the second type of conductivity, extending into the interior of the JFET region. An isolated gate structure lies partially over the first body region, the first source region and the JFET region. A first metallization layer extends over the first surface and forms, in direct contact with the implanted structure and with the JFET region, a JBS diode.