公开(公告)号：US20160181381A1

公开(公告)日：2016-06-23

申请号：US14577431

申请日：2014-12-19

Applicant: STMicroelectronics, Inc. ,  International Business Machines Corporation ,  GlobalFoundries Inc

Inventor： Qing Liu ,  Xiuyu Cai ,  Ruilong Xie ,  Chun-Chen Yeh

IPC: H01L29/417 ,  H01L29/66 ,  H01L29/06 ,  H01L29/78

CPC classification number: H01L29/41783 ,  H01L29/0653 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785

Abstract: A FinFET device includes a semiconductor fin, a gate electrode extending over a channel of the fin and sidewall spacers on each side of the gate electrode. A dielectric material is positioned on each side of a bottom portion of said fin, with an oxide material on each side of the fin overlying the dielectric material. A recessed region, formed in the fin on each side of the channel region, is delimited by the oxide material. A raised source region fills the recessed region and extends from the fin on a first side of the gate electrode to cover the oxide material to a height which is in contact with the sidewall spacer. A raised drain region fills the recessed region and extends from the fin on a second side of the gate electrode to cover the oxide material to a height which is in contact with the sidewall spacer.

Abstract translation: FinFET器件包括半导体鳍片，在鳍片的沟道上延伸的栅极电极和在栅电极的每一侧上的侧壁间隔物。 电介质材料位于所述散热片的底部的每一侧上，其中在散热片的每侧的氧化物材料覆盖在电介质材料上。 在通道区域的每一侧的翅片上形成的凹陷区域由氧化物材料界定。 凸起的源极区域填充凹陷区域并且在栅电极的第一侧上从翅片延伸以将氧化物材料覆盖到与侧壁间隔物接触的高度。 凸起的漏极区域填充凹陷区域并且在栅电极的第二侧上从翅片延伸以将氧化物材料覆盖到与侧壁间隔物接触的高度。

公开(公告)号：US09368411B2

公开(公告)日：2016-06-14

申请号：US14596625

申请日：2015-01-14

Applicant: STMicroelectronics, Inc.

Inventor： Nicolas Loubet ,  Qing Liu

IPC: H01L21/8238 ,  H01L21/02 ,  H01L21/84

CPC classification number: H01L21/823807 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/02664 ,  H01L21/823821 ,  H01L21/845

Abstract: A SOI substrate layer formed of a silicon semiconductor material includes adjacent first and second regions. A portion of the silicon substrate layer in the second region is removed such that the second region retains a bottom portion made of the silicon semiconductor material. An epitaxial growth of a silicon-germanium semiconductor material is made on the bottom portion to produce a silicon-germanium region. The silicon region is patterned to define a first fin structure of a FinFET of a first (for example, n-channel) conductivity type. The silicon-germanium region is also patterned to define a second fin structure of a FinFET of a second (for example, p-channel) conductivity type.

Abstract translation: 由硅半导体材料形成的SOI衬底层包括相邻的第一和第二区域。 去除第二区域中的硅衬底层的一部分，使得第二区域保持由硅半导体材料制成的底部。 硅 - 锗半导体材料的外延生长在底部制成以产生硅 - 锗区。 图案化硅区域以限定第一（例如，n沟道）导电类型的FinFET的第一鳍结构。 硅 - 锗区域也被图案化以限定第二（例如p沟道）导电类型的FinFET的第二鳍结构。

公开(公告)号：US20160163850A1

公开(公告)日：2016-06-09

申请号：US14560255

申请日：2014-12-04

Applicant: STMicroelectronics, Inc. ,  International Business Machines Corporation ,  GlobalFoundries Inc

Inventor： Qing Liu ,  Ruilong Xie ,  Chun-Chen Yeh ,  Xiuyu Cai

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/417 ,  H01L27/092 ,  H01L29/08

CPC classification number: H01L29/785 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/845 ,  H01L27/0886 ,  H01L27/1211 ,  H01L29/086 ,  H01L29/0869 ,  H01L29/0878 ,  H01L29/0886 ,  H01L29/41758 ,  H01L29/41791 ,  H01L29/66545 ,  H01L29/66659 ,  H01L29/66681 ,  H01L29/66795 ,  H01L29/7816 ,  H01L29/7835 ,  H01L29/7848

Abstract: A FinFET transistor includes a fin of semiconductor material with a transistor gate electrode extending over a channel region. Raised source and drain regions of first epitaxial growth material extending from the fin on either side of the transistor gate electrode. Source and drain contact openings extend through a pre-metallization dielectric material to reach the raised source and drain regions. Source and drain contact regions of second epitaxial growth material extend from the first epitaxial growth material at the bottom of the source and drain contact openings. A metal material fills the source and drain contact openings to form source and drain contacts, respectively, with the source and drain contact regions. The drain contact region may be offset from the transistor gate electrode by an offset distance sufficient to provide a laterally diffused metal oxide semiconductor (LDMOS) configuration within the raised source region of first epitaxial growth material.

Abstract translation: FinFET晶体管包括具有在沟道区域上延伸的晶体管栅电极的半导体材料的鳍。 从晶体管栅电极的两侧的鳍延伸的第一外延生长材料的引出源区和漏区。 源极和漏极接触开口延伸穿过预金属化电介质材料以到达升高的源极和漏极区域。 第二外延生长材料的源极和漏极接触区域在源极和漏极接触开口的底部处从第一外延生长材料延伸。 金属材料填充源极和漏极接触开口，以分别与源极和漏极接触区域形成源极和漏极接触。 漏极接触区域可以从晶体管栅电极偏移足以在第一外延生长材料的升高的源极区域内提供横向扩散的金属氧化物半导体（LDMOS）配置的偏移距离。

公开(公告)号：US09357635B2

公开(公告)日：2016-05-31

申请号：US14981056

申请日：2015-12-28

Applicant: STMicroelectronics, Inc. ,  STMicroelectronics S.r.l. ,  STMicroelectronics Asia Pacific Pte Ltd

Inventor： Simon Dodd ,  Joe Scheffelin ,  Dana Gruenbacher ,  Roberto Brioschi ,  Teck Khim Neo ,  Dave Hunt ,  Faiz Sherman

IPC: B41J2/14 ,  B41J2/175 ,  B05B1/14 ,  B32B38/04 ,  B32B38/14 ,  B32B37/00 ,  H05K1/02 ,  H05K1/09 ,  H05K3/30

CPC classification number: B41J2/1623 ,  B05B1/14 ,  B05B11/0054 ,  B05B15/40 ,  B41J2/14024 ,  B41J2/14145 ,  B41J2/1433 ,  B41J2/162 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L24/83 ,  H01L24/85 ,  H01L24/97 ,  H01L41/1132 ,  H01L2224/2732 ,  H01L2224/29011 ,  H01L2224/29013 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/48096 ,  H01L2224/48097 ,  H01L2224/48106 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/83192 ,  H01L2224/838 ,  H01L2224/83862 ,  H01L2224/83874 ,  H01L2224/92247 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/19106 ,  H05K1/0272 ,  H05K1/09 ,  H05K1/181 ,  H05K3/305 ,  H05K2201/10083 ,  H05K2201/10515 ,  H05K2201/10545 ,  Y02P70/613 ,  Y10T156/1089 ,  H01L2224/83 ,  H01L2224/85 ,  H01L2224/45099 ,  H01L2924/00

Abstract: Embodiments are directed to microfluidic refill cartridges and methods of assembling same. The microfluidic refill cartridges include a microfluidic delivery member that includes a filter for filtering fluid passed therethrough. The filter may be configured to block particles above a threshold size to prevent blockage in the nozzles. For instances, particles having a dimension that is larger than the diameter of the nozzles can block or reduce fluid flow through the nozzle.

Abstract translation: 实施例涉及微流体补充盒及其组装方法。 微流体补充盒包括微流体递送构件，其包括用于过滤通过其中的流体的过滤器。 过滤器可以被配置为阻挡高于阈值尺寸的颗粒以防止喷嘴中的堵塞。 例如，具有大于喷嘴直径的尺寸的颗粒可阻挡或减少通过喷嘴的流体流动。

公开(公告)号：US20160149500A1

公开(公告)日：2016-05-26

申请号：US15011854

申请日：2016-02-01

Applicant: STMicroelectronics, Inc.

Inventor： Thomas Stamm

IPC: H02M3/335 ,  H05B33/08 ,  H02M1/42

CPC classification number: H02M3/33515 ,  H02M1/42 ,  H02M7/217 ,  H05B33/0815 ,  Y02B20/347

Abstract: A fly-back type switched current regulator includes a primary transformer winding coupled to receive a rectified DC signal derived from an AC signal. The drain of a power transistor is coupled to the primary winding, with the source of the power transistor coupled to an input of a comparison circuit and a primary transformer winding sense resistor. A control terminal of the power transistor is coupled to an output of the comparison circuit. A capacitor stores a variable reference signal for application at a first capacitor terminal to another input of the differential circuit. The variable reference signal is compared to a winding current signal generated by the sense resistor by the comparison circuit. An injection circuit applies an AC signal derived from the rectified DC signal to a second terminal of the capacitor so as to modulate the stored variable reference signal. The regulator is coupled to drive LEDs.

Abstract translation: 回扫式开关电流调节器包括耦合以接收从AC信号导出的整流DC信号的初级变压器绕组。 功率晶体管的漏极耦合到初级绕组，功率晶体管的源极耦合到比较电路的输入端和初级变压器绕组检测电阻器。 功率晶体管的控制端耦合到比较电路的输出端。 电容器存储用于在第一电容器端子处施加到差分电路的另一输入端的可变参考信号。 可变参考信号与由比较电路由检测电阻器产生的绕组电流信号进行比较。 注入电路将从整流后的直流信号得到的交流信号施加到电容器的第二端，以便调制存储的可变参考信号。 调节器耦合到驱动LED。

公开(公告)号：US09340023B2

公开(公告)日：2016-05-17

申请号：US13906447

申请日：2013-05-31

Applicant: STMICROELECTRONICS, INC.

Inventor： Paul I. Mikulan ,  Kenneth J. Stewart ,  Virgina L. Hwang

IPC: B41J2/16

CPC classification number: B41J2/1603 ,  B41J2/1601 ,  B41J2/1628 ,  B41J2/1629 ,  B41J2/1631 ,  B41J2/1635 ,  B41J2/1637 ,  B41J2/1639 ,  Y10T29/49083 ,  Y10T29/49087 ,  Y10T29/49401

Abstract: A method of making inkjet print heads may include forming a first wafer including a sacrificial substrate layer, and a first dielectric layer thereon having first openings therein defining inkjet orifices. The method may also include forming a second wafer having inkjet chambers defined thereon, and joining the first and second wafers together so that each inkjet orifice is aligned with a respective inkjet chamber. The method may further include removing the sacrificial substrate layer thereby defining the inkjet print heads.

Abstract translation: 制造喷墨打印头的方法可以包括形成包括牺牲基底层的第一晶片和其上具有限定喷墨孔的第一开口的第一介电层。 该方法还可以包括形成具有限定在其上的喷墨室的第二晶片，并且将第一和第二晶片接合在一起，使得每个喷墨孔与相应的喷墨室对准。 该方法还可以包括去除牺牲衬底层从而限定喷墨打印头。

公开(公告)号：US09337087B1

公开(公告)日：2016-05-10

申请号：US14586688

申请日：2014-12-30

Applicant: STMicroelectronics, Inc. ,  International Business Machines Corporation

Inventor： John H. Zhang ,  Lawrence A. Clevenger ,  Carl Radens ,  Yiheng Xu ,  Byoung Youp Kim ,  Walter Kleemeier

IPC: H01L21/4763 ,  H01L21/768 ,  H01L23/522

CPC classification number: H01L23/562 ,  H01L21/76805 ,  H01L21/76843 ,  H01L21/76897 ,  H01L22/12 ,  H01L22/14 ,  H01L22/32 ,  H01L23/5223 ,  H01L23/5226 ,  H01L23/5227 ,  H01L23/5228 ,  H01L23/528 ,  H01L23/53266 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Various embodiments facilitate die protection for an integrated circuit. In one embodiment, a multilayer structure is formed in multiple levels and along the edges of a die to prevent and detect damages to the die. The multilayer structure includes a support layer, a first plurality of dielectric pillars overlying the support layer, a metal layer that fills spaces between the first plurality of dielectric pillars, an insulation layer overlying the first plurality of dielectric pillars and the metal layer, a second plurality of dielectric pillars overlying the insulation layer, and a second metal layer that fills spaces between the second plurality of dielectric pillars.

Abstract translation: 各种实施例便于集成电路的管芯保护。 在一个实施例中，多层结构形成在多个层次上并沿着模具的边缘，以防止和检测对模具的损坏。 所述多层结构包括支撑层，覆盖所述支撑层的第一多个介电柱，填充所述第一多个介电柱之间的空间的金属层，覆盖所述第一多个介电柱和所述金属层的绝缘层，第二 覆盖绝缘层的多个介电柱，以及填充第二多个介电柱之间的空间的第二金属层。

公开(公告)号：US20160118305A1

公开(公告)日：2016-04-28

申请号：US14942504

申请日：2015-11-16

Applicant: STMicroelectronics, Inc.

Inventor： Walter Kleemeier ,  Qing Liu

IPC: H01L21/8238 ,  H01L29/78 ,  H01L21/84 ,  H01L21/02 ,  H01L29/66

CPC classification number: H01L21/823814 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/02584 ,  H01L21/8238 ,  H01L21/823821 ,  H01L21/823871 ,  H01L21/84 ,  H01L27/092 ,  H01L27/0924 ,  H01L27/1203 ,  H01L27/1211 ,  H01L29/45 ,  H01L29/456 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/66628 ,  H01L29/778 ,  H01L29/7789 ,  H01L29/7838

Abstract: An integrated circuit includes a substrate supporting a transistor having a source region and a drain region. A high dopant concentration delta-doped layer is present on the source region and drain region of the transistor. A set of contacts extend through a pre-metal dielectric layer covering the transistor. A silicide region is provided at a bottom of the set of contacts. The silicide region is formed by a salicidation reaction between a metal present at the bottom of the contact and the high dopant concentration delta-doped layer on the source region and drain region of the transistor.

Abstract translation: 集成电路包括支撑具有源极区和漏极区的晶体管的衬底。 晶体管的源极区和漏极区存在高掺杂浓度的δ掺杂层。 一组触点延伸穿过覆盖晶体管的预金属介电层。 硅化物区域设置在该组触点的底部。 硅化物区域由接触底部存在的金属与晶体管的源极区域和漏极区域上的高掺杂浓度δ-掺杂层之间的水化反应形成。

公开(公告)号：US09325492B2

公开(公告)日：2016-04-26

申请号：US12660952

申请日：2010-03-08

Applicant: Kurt Godwin

Inventor： Kurt Godwin

IPC: H04K1/04 ,  H04L9/00

CPC classification number: H04L9/00

Abstract: A system and method for improving performance while transferring encrypted data in an input/output (I/O) operation are provided. The method includes receiving a block of data. The method also includes dividing the block of data into a plurality of sub-blocks of data. The method further includes performing a first operation on a first sub-block. The method also includes performing a second operation on a second sub-block at substantially the same time as performing the first operation on the first sub-block. The method still further includes reassembling the plurality of sub-blocks into the block of data.

Abstract translation: 提供了一种用于在输入/输出（I / O）操作中传送加密数据时提高性能的系统和方法。 该方法包括接收数据块。 该方法还包括将数据块划分成多个数据子块。 该方法还包括对第一子块执行第一操作。 该方法还包括在与第一子块执行第一操作基本相同的时间对第二子块执行第二操作。 该方法还包括将多个子块重新组合到数据块中。

公开(公告)号：US09323633B2

公开(公告)日：2016-04-26

申请号：US13852223

申请日：2013-03-28

Applicant: STMICROELECTRONICS, INC.

Inventor： Marco Brambilla ,  Ulderic Lacour ,  Cecilia Ozdemir

IPC: G06F11/00 ,  G06F11/25 ,  G01R31/3177 ,  G06F11/267

CPC classification number: G06F11/267

Abstract: A dual-master controller includes a plurality of JTAG data registers including a controller-mode register that stores information indicating a standard JTAG or a processor-controlled mode of operation. A JTAG TAP controller receives control signals over a standard test access port and a processor controller receives processor control signals over an external processor bus. A selection multiplexer outputs either signals on the standard JTAG access port or the external processor bus responsive to a JTAG mode selection signal. A logic circuit activates the JTAG mode selection signal responsive to the force JTAG signal being active or information in the controller-mode register indicating the standard JTAG mode, and deactivates the JTAG mode selection signal responsive to the force JTAG signal being deactivated or the information in the controller-mode register indicating the processor-controller mode. An instruction decoder and multiplexer circuit applies control signals from the selection multiplexer to control the JTAG data registers.

Abstract translation: 双主控制器包括多个JTAG数据寄存器，包括存储指示标准JTAG或处理器控制的操作模式的信息的控制器模式寄存器。 JTAG TAP控制器通过标准测试访问端口接收控制信号，处理器控制器通过外部处理器总线接收处理器控制信号。 响应于JTAG模式选择信号，选择多路复用器输出标准JTAG访问端口或外部处理器总线上的信号。 逻辑电路响应于JTAG信号被激活或控制器模式寄存器中指示标准JTAG模式的信息激活JTAG模式选择信号，并且响应于JTAG信号被去激活而停用JTAG模式选择信号 控制器模式寄存器指示处理器 - 控制器模式。 指令解码器和多路复用器电路从选择多路复用器施加控制信号以控制JTAG数据寄存器。