公开(公告)号：US09240466B2

公开(公告)日：2016-01-19

申请号：US14451174

申请日：2014-08-04

Applicant: STMicroelectronics SA ,  STMicroelectronics, Inc.

Inventor： Pierre Morin ,  Denis Rideau ,  Olivier Nier

IPC: H01L21/00 ,  H01L29/66 ,  H01L21/02 ,  H01L21/324 ,  H01L21/762 ,  H01L29/78 ,  H01L27/12

CPC classification number: H01L29/66772 ,  H01L21/0217 ,  H01L21/324 ,  H01L21/76283 ,  H01L21/84 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/66795 ,  H01L29/7843 ,  H01L29/7847 ,  H01L29/785

Abstract: The disclosure concerns a method of stressing a semiconductor layer comprising: forming, over a silicon on insulator structure having a semiconductor layer in contact with an insulating layer, one or more stressor blocks aligned with first regions of said semiconductor layer in which transistor channels are to be formed, wherein said stressor blocks are stressed such that they locally stress said semiconductor layer; and deforming second regions of said insulating layer adjacent to said first regions by temporally decreasing, by annealing, the viscosity of said insulator layer.

Abstract translation: 本公开涉及一种对半导体层施加应力的方法，包括：在绝缘体上的结构上形成绝缘体结构，该绝缘体上硅结构具有与绝缘层相接触的半导体层，一个或多个与晶体管沟道所在半导体层的第一区对准的应力块 形成，其中所述应力块被应力，使得它们局部应力所述半导体层; 以及通过退火所述绝缘体层的粘度暂时减小所述绝缘层的与所述第一区域相邻的第二区域。

公开(公告)号：US09236909B2

公开(公告)日：2016-01-12

申请号：US14559756

申请日：2014-12-03

Applicant: STMicroelectronics, Inc.

Inventor： Oleg Logvinov

IPC: H04L25/00 ,  H04B3/54 ,  H04L12/10 ,  H04L12/28

CPC classification number: H04L12/10 ,  G06F1/3209 ,  G06F1/3287 ,  H04B3/542 ,  H04L12/2838 ,  H04L2012/2843 ,  Y02D10/171

Abstract: An embodiment is an integrated System on Chip (SoC) including a communication interface configured to implement a communication protocol including functional blocks that are energized or de-energized individually so that a minimum power consumption is used to receive and detect a signal, and a receiver identification (ID) detection function configured to determine whether the signal is intended for the device in which the SoC resides. The SoC further includes a power management function configured to control which functions in the SoC and/or device in which the SoC resides are energized or de-energized depending on the results of the receiver ID detection function, and a power source capable of energizing a minimum number of the functional blocks required to receive and detect a signal, wherein the power source can be used in a low power state and switched over to a main power supply when the SoC is energized.

Abstract translation: 一个实施例是集成片上系统（SoC），其包括通信接口，该通信接口被配置为实现包括被单独通电或断电的功能块的通信协议，以便使用最小功耗来接收和检测信号，以及接收器 识别（ID）检测功能，被配置为确定信号是否适用于SoC驻留的设备。 SoC还包括功率管理功能，其被配置为根据接收机ID检测功能的结果来控制SoC驻留的SoC和/或设备中的哪些功能被激励或断电，以及能够激励 接收和检测信号所需的功能块的最小数量，其中当SoC被通电时，电源可以以低功率状态使用并切换到主电源。

公开(公告)号：US09232469B2

公开(公告)日：2016-01-05

申请号：US14025456

申请日：2013-09-12

Applicant: STMicroelectronics, Inc.

Inventor： Liwen Chu ,  George A. Vlantis

IPC: G08C17/00 ,  H04W52/02

CPC classification number: H04W52/0209 ,  H04W52/0219 ,  Y02D70/142

Abstract: An additional cyclic redundancy check (CRC) is inserted in IEEE 802.11 beacon or data frames prior to the end of the frame, at a location following information sufficient for the receiving station to determine whether the frame is from an overlapping basic service set or intended for a different station and to extract other necessary or useful information such as a time of the next full beacon. Upon detecting the CRC, the receiving STA can terminate reception of the frame early to conserve power, and then enter a low power operational mode to further conserve power.

Abstract translation: 在足以使接收站确定帧是否来自重叠的基本业务集或旨在为重叠的基本业务集合的信息之后的位置处，在帧的结尾之前的IEEE 802.11信标或数据帧中插入附加的循环冗余校验（CRC） 一个不同的站，并提取其他必要或有用的信息，如下一个完整信标的时间。 在检测到CRC时，接收STA可以提前终止帧的接收以节省功率，然后进入低功率操作模式以进一步节省功率。

公开(公告)号：US20150380258A1

公开(公告)日：2015-12-31

申请号：US14314384

申请日：2014-06-25

Applicant: STMicroelectronics, Inc. ,  International Business Machines Corporation ,  GLOBALFOUNDRIES Inc.

Inventor： Qing Liu ,  Ruilong Xie ,  Xiuyu Cai ,  Chun-chen Yeh ,  Kejia Wang

IPC: H01L21/308 ,  H01L29/205 ,  H01L29/78

CPC classification number: H01L29/205 ,  H01L29/1054 ,  H01L29/66795 ,  H01L29/785

Abstract: Methods and structures for forming fin structures whilst controlling the height of the fin structures with high uniformity across large areas are described. According to some aspects, a multi-layer structure comprising a first etch-stop layer and a second etch-stop layer separated from a substrate and from each other by spacer layers is formed on a substrate. Trenches may be formed through the first and second etch-stop layers. A buffer layer may be formed in the trenches, filling the trenches to a level approximately at a position of the first etch-stop layer. A semiconductor layer may be formed above the buffer layer and etched back to the second etch-stop layer to form semiconductor fins of highly uniform heights.

Abstract translation: 描述了形成翅片结构的方法和结构，同时在大面积上以高均匀性控制翅片结构的高度。 根据一些方面，在衬底上形成包括由衬底分离并通过间隔层彼此分离的第一蚀刻停止层和第二蚀刻停止层的多层结构。 沟槽可以通过第一和第二蚀刻停止层形成。 可以在沟槽中形成缓冲层，将沟槽填充到大致在第一蚀刻停止层的位置处的水平。 半导体层可以形成在缓冲层的上方并被回蚀刻到第二蚀刻停止层以形成高均匀高度的半导体鳍片。

公开(公告)号：US20150357477A1

公开(公告)日：2015-12-10

申请号：US14298000

申请日：2014-06-06

Applicant: STMicroelectronics, Inc.

Inventor： John Hongguang Zhang ,  Walter Kleemeier

IPC: H01L29/786 ,  H01L27/12

CPC classification number: H01L29/41766 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/41733 ,  H01L29/4975 ,  H01L29/78603 ,  H01L29/78648

Abstract: An integrated circuit transistor is formed on and in a substrate. A trench in the substrate is at least partially filed with a metal material to form a source (or drain) contact buried in the substrate. The substrate further includes a source (or drain) region epitaxially grown above the source (or drain) contact. The substrate further includes a channel region adjacent to the source (or drain) region. A gate dielectric is provided on top of the channel region and a gate electrode is provided on top of the gate dielectric. The substrate is preferably of the silicon on insulator (SOI) type.

Abstract translation: 集成电路晶体管形成在衬底上和衬底中。 衬底中的沟槽至少部分地与金属材料填充以形成埋在衬底中的源极（或漏极）接触。 衬底还包括在源极（或漏极）触点上方外延生长的源极（或漏极）区域。 衬底还包括与源极（或漏极）区域相邻的沟道区域。 栅极电介质设置在沟道区域的顶部，栅电极设置在栅极电介质的顶部。 衬底优选为绝缘体上硅（SOI）型。

公开(公告)号：US20150351234A1

公开(公告)日：2015-12-03

申请号：US14294875

申请日：2014-06-03

Applicant: STMicroelectronics, Inc.

Inventor： Rammil Seguido ,  Frederick Ray Gomez ,  Emmanuel Angeles

IPC: H05K1/02 ,  H05K1/18 ,  H05K1/11 ,  H05K3/30

CPC classification number: H05K1/0296 ,  H01L23/66 ,  H01L25/0652 ,  H01L2224/48091 ,  H01L2224/73265 ,  H05K1/0271 ,  H05K1/111 ,  H05K1/181 ,  H05K3/305 ,  H05K2201/09236 ,  H05K2201/09781 ,  H05K2201/10378 ,  H05K2201/10515 ,  H05K2201/1053 ,  H05K2201/10719 ,  H05K2201/10977 ,  H05K2203/049 ,  Y10T29/49146 ,  H01L2924/00014

Abstract: Delamination of stacked integrated circuit die configurations on printed circuit boards is avoided by providing a metal trace support structure underneath the die stack. The metal trace support structure features substantially equally spaced thin metal traces in place of a contiguous metal plate which has been used in the past. Spaced apart thin metal traces are less vulnerable to thermal expansion than a metal plate which has a large thermal mass. The metal traces still provide structural stability, while preventing delamination of the die stack configuration during thermal processing. A method of attaching a bridge die stack configuration to a printed circuit board by adhering a die attach film to a field of metal traces is demonstrated. In addition, the electrical and structural integrity of the bridge die stack formed with a metal trace support structure is confirmed with test results.

Abstract translation: 通过在管芯堆叠下方提供金属迹线支撑结构，可以避免印刷电路板上的堆叠集成电路管芯结构的分层。 金属迹线支撑结构具有基本相等间隔的细金属迹线，代替过去使用的连续金属板。 分隔开的薄金属迹线比具有大热质量的金属板不易受热膨胀。 金属迹线仍然提供结构稳定性，同时防止热处理期间芯片堆叠配置的分层。 证明了通过将管芯附着膜粘附到金属痕迹的领域将桥模组叠构造附着到印刷电路板的方法。 此外，用测试结果证实了由金属迹线支撑结构形成的桥模组的电气和结构完整性。

公开(公告)号：US20150348851A1

公开(公告)日：2015-12-03

申请号：US14822959

申请日：2015-08-11

Applicant: STMicroelectronics, Inc.

Inventor： Ronald K. Sampson ,  Nicolas Loubet

IPC: H01L21/84 ,  H01L29/10 ,  H01L21/02 ,  H01L21/28 ,  H01L29/66 ,  H01L29/06

CPC classification number: H01L27/1211 ,  H01L21/0217 ,  H01L21/02271 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/0257 ,  H01L21/26513 ,  H01L21/28035 ,  H01L21/3081 ,  H01L21/845 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0673 ,  H01L29/1083 ,  H01L29/167 ,  H01L29/4916 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785

Abstract: A semiconductor material is patterned to define elongated fins insulated from an underlying substrate. A polysilicon semiconductor material is deposited over and in between the elongated fins, and is patterned to define elongated gates extending to perpendicularly cross over the elongated fins at a transistor channel. Sidewall spacers are formed on side walls of the elongated gates. Portions of the elongated fins located between the elongated gates are removed, along with the underlying insulation, to expose the underlying substrate. One or more semiconductor material layers are then epitaxially grown from the underlying substrate at locations between the elongated gates. The one or more semiconductor material layers may include an undoped epi-layer and an overlying doped epi-layer. The epitaxial material defines a source or drain of the transistor.

Abstract translation: 将半导体材料图案化以限定与底层基板绝缘的细长翅片。 多晶硅半导体材料沉积在细长翅片之上并在细长翅片之间，并且被图案化以限定延伸到在晶体管沟槽处垂直交叉在细长翅片上的细长门。 侧壁间隔件形成在细长门的侧壁上。 位于细长门之间的细长翅片的部分与下面的绝缘体一起被去除以暴露下面的基底。 然后在细长门之间的位置从下面的衬底外延生长一个或多个半导体材料层。 一个或多个半导体材料层可以包括未掺杂的外延层和上覆的掺杂外延层。 外延材料限定晶体管的源极或漏极。

公开(公告)号：US09202920B1

公开(公告)日：2015-12-01

申请号：US14447727

申请日：2014-07-31

Applicant: STMicroelectronics, Inc. ,  International Business Machines Corporation ,  GLOBALFOUNDRIES Inc.

Inventor： Qing Liu ,  Chun-chen Yeh ,  Ruilong Xie ,  Xiuyu Cai

IPC: H01L29/78 ,  H01L29/66

CPC classification number: H01L29/785 ,  H01L29/66553 ,  H01L29/66795 ,  H01L29/7848

Abstract: Methods and structures for forming short-channel finFETs with vertical and abrupt source and drain junctions are described. During fabrication, source and drain regions of the finFET may be recessed vertically and laterally under gate spacers. A buffer having a high dopant density may be formed on vertical sidewalls of the channel region after recessing the fin. Raised source and drain structures may be formed at the recessed source and drain regions. The raised source and drain structures may impart strain to the channel region.

Abstract translation: 描述了用于形成具有垂直和突然的源极和漏极结的短沟道finFET的方法和结构。 在制造期间，finFET的源极和漏极区域可以在栅极间隔物下方垂直和横向地凹陷。 具有高掺杂浓度的缓冲器可以在凹陷鳍片之后形成在沟道区域的垂直侧壁上。 可以在凹陷的源极和漏极区域形成升高的源极和漏极结构。 升高的源极和漏极结构可能对沟道区域施加应变。

公开(公告)号：US09197934B2

公开(公告)日：2015-11-24

申请号：US13474286

申请日：2012-05-17

Applicant: Steven Srebranig

Inventor： Steven Srebranig

IPC: H04N21/4425 ,  H04N21/426 ,  H04N21/61 ,  H04H40/90 ,  H04H20/12 ,  G06F11/18

CPC classification number: H04N21/4425 ,  G06F11/184 ,  H04H20/12 ,  H04H40/90 ,  H04N21/42607 ,  H04N21/6112 ,  H04N21/6143

Abstract: A system includes a primary functionality and a backup functionality for the primary functionality. A measurement circuit measures operational parameter values of the primary functionality. A fault detection circuit determines a level of equivalence between the operation of the primary functionality and a reference functionality based on a weighted comparison of the measured operational parameter values of the primary functionality to corresponding reference operational parameter values for the reference functionality If the equivalence determination fails to find equivalence, the fault detection circuit signals a fault in the primary functionality and activates the backup functionality.

Abstract translation: 系统包括主要功能和主要功能的备份功能。 测量电路测量主要功能的操作参数值。 故障检测电路基于主要功能的测量的操作参数值与参考功能的相应参考操作参数值的加权比较来确定主要功能的操作与参考功能之间的等同水平。如果等效确定失败 为了找到等效性，故障检测电路发出主要功能中的故障，并激活备份功能。

公开(公告)号：US09190517B2

公开(公告)日：2015-11-17

申请号：US14518590

申请日：2014-10-20

Applicant: STMICROELECTRONICS, INC. ,  INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Nicolas Loubet ,  Douglas Latulipe ,  Alexander Reznicek

IPC: H01L29/78 ,  H01L27/092 ,  H01L29/417 ,  H01L29/165 ,  H01L29/66

CPC classification number: H01L29/7848 ,  H01L21/823425 ,  H01L27/092 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/41783 ,  H01L29/4958 ,  H01L29/66628 ,  H01L29/66636

Abstract: A method for making a semiconductor device includes forming at least one gate stack on a layer comprising a first semiconductor material and etching source and drain recesses adjacent the at least one gate stack. The method further includes shaping the source and drain recesses to have a vertical side extending upwardly from a bottom to an inclined extension adjacent the at least one gate stack.

Abstract translation: 制造半导体器件的方法包括在包括第一半导体材料的层上形成至少一个栅极堆叠，以及邻近所述至少一个栅极堆叠的蚀刻源极和漏极凹陷。 该方法进一步包括成形源极和漏极凹槽以具有从底部向上延伸到与所述至少一个栅极堆叠相邻的倾斜延伸部的垂直侧。