公开(公告)号：US20150255295A1

公开(公告)日：2015-09-10

申请号：US14197790

申请日：2014-03-05

Applicant: GLOBALFOUNDRIES Inc. ,  STMicroelectronics, Inc. ,  International Business Machines Corporation

Inventor： Ajey Poovannummoottil Jacob ,  Bruce Doris ,  Kangguo Cheng ,  Nicolas Loubet

IPC: H01L21/28 ,  H01L21/762 ,  H01L29/66

CPC classification number: H01L21/76224 ,  H01L29/045 ,  H01L29/165 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7853

Abstract: One illustrative method disclosed herein involves, among other things, forming trenches to form an initial fin structure having an initial exposed height and sidewalls, forming a protection layer on at least the sidewalls of the initial fin structure, extending the depth of the trenches to thereby define an increased-height fin structure, with a layer of insulating material over-filling the final trenches and with the protection layer in position, performing a fin oxidation thermal anneal process to convert at least a portion of the increased-height fin structure into an isolation material, removing the protection layer, and performing an epitaxial deposition process to form a layer of semiconductor material on at least portions of the initial fin structure.

Abstract translation: 本文中公开的一种说明性方法包括形成沟槽以形成具有初始暴露高度和侧壁的初始鳍结构，在至少初始鳍结构的侧壁上形成保护层，从而延伸沟槽的深度，从而 限定一个增加高度的翅片结构，其中绝缘材料层覆盖最终的沟槽并且将保护层置于适当位置，执行翅片氧化热退火工艺以将至少一部分高度翅片结构转换为 隔离材料，去除保护层，以及进行外延沉积工艺以在初始鳍结构的至少部分上形成半导体材料层。

公开(公告)号：US20150249153A1

公开(公告)日：2015-09-03

申请号：US14194215

申请日：2014-02-28

Applicant: STMicroelectronics, Inc.

Inventor： Pierre Morin ,  Nicolas Loubet

IPC: H01L29/78 ,  H01L29/66

CPC classification number: H01L27/10879 ,  H01L21/2251 ,  H01L29/0649 ,  H01L29/1054 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/165 ,  H01L29/41791 ,  H01L29/4236 ,  H01L29/66772 ,  H01L29/66795 ,  H01L29/7825 ,  H01L29/7838 ,  H01L29/7849 ,  H01L29/785 ,  H01L29/7855 ,  H01L29/78603 ,  H01L29/78654

Abstract: Methods and structures for forming a localized, strained region of a substrate are described. Trenches may be formed at boundaries of a localized region of a substrate. An upper portion of sidewalls at the localized region may be covered with a covering layer, and a lower portion of the sidewalls at the localized region may not be covered. A converting material may be formed in contact with the lower portion of the localized region, and the substrate heated. The heating may introduce a chemical species from the converting material into the lower portion, which creates stress in the localized region. The methods may be used to form strained-channel finFETs.

Abstract translation: 描述了形成基底的局部应变区域的方法和结构。 可以在衬底的局部区域的边界处形成沟槽。 局部区域的侧壁的上部可以被覆盖层覆盖，并且局部区域的侧壁的下部可能不被覆盖。 可以将转换材料形成为与局部区域的下部接触，并且加热衬底。 加热可以将化学物质从转化材料引入下部，这在局部区域中产生应力。 这些方法可以用于形成应变通道的finFET。

公开(公告)号：US09123809B2

公开(公告)日：2015-09-01

申请号：US14494979

申请日：2014-09-24

Applicant: STMicroelectronics, Inc.

Inventor： Nicolas Loubet ,  Prasanna Khare ,  Qing Liu

IPC: H01L29/76 ,  H01L29/78 ,  H01L21/265 ,  H01L29/66 ,  H01L21/8238 ,  H01L21/84 ,  H01L27/12 ,  H01L21/266 ,  H01L21/762 ,  H01L29/06

CPC classification number: H01L29/7848 ,  H01L21/26506 ,  H01L21/266 ,  H01L21/76224 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823878 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/0649 ,  H01L29/66628 ,  H01L29/7849

Abstract: A transistor includes a body and a semiconductor region configured to stress a portion of the body. For example, stressing a channel of the transistor may increase the mobility of carriers in the channel, and thus may reduce the “on” resistance of the transistor. For example, the substrate, source/drain regions, or both the substrate and source/drain regions of a PFET may be doped to compressively stress the channel so as to increase the mobility of holes in the channel. Or, the substrate, source/drain regions, or both the substrate and source/drain regions of an NFET may be doped to tensile stress the channel so as to increase the mobility of electrons in the channel.

Abstract translation: 晶体管包括主体和构造成对身体的一部分施加应力的半导体区域。 例如，施加晶体管的沟道可以增加沟道中载流子的迁移率，从而可以降低晶体管的“导通”电阻。 例如，可以掺杂PFET的衬底，源极/漏极区域或者衬底和源/漏极区域，以对沟道进行压缩应力，从而增加沟道中空穴的迁移率。 或者，可以掺杂NFET的衬底，源极/漏极区域或衬底和源极/漏极区域两者以使通道拉伸应力，以增加沟道中电子的迁移率。

公开(公告)号：US20150243510A1

公开(公告)日：2015-08-27

申请号：US14187598

申请日：2014-02-24

Applicant: STMicroelectronics, Inc. ,  International Business Machines Corporation

Inventor： Lawrence A. Clevenger ,  Carl J. Radens ,  Richard S. Wise ,  Edem Wornyo ,  Yiheng Xu ,  John Zhang

IPC: H01L21/308

CPC classification number: H01L29/0661 ,  H01L21/02071 ,  H01L21/0337 ,  H01L21/3085 ,  H01L21/3086 ,  H01L21/31138 ,  H01L21/31144 ,  H01L21/32139 ,  H01L29/66621 ,  H01L29/66795 ,  H01L51/0525

Abstract: An ashing chemistry employing a combination of Cl2 and N2 is provided, which removes residual material from sidewalls of a patterned metallic hard mask layer without residue such that the sidewalls of the patterned metallic hard mask layer are vertical. The vertical profiled of the sidewalls of the patterned metallic hard mask layer can be advantageously employed to reduce pattern factor dependency in the etch bias between the pattern transferred into an underlying layer and the pattern as formed on the metallic hard mask layer. Further, the ashing chemistry can be employed to enhance removal of stringers in vertical portions of a metallic material layer.

Abstract translation: 提供采用Cl 2和N 2的组合的灰化化学品，其从图案化的金属硬掩模层的侧壁除去剩余材料，而不残留物，使得图案化的金属硬掩模层的侧壁是垂直的。 图案化的金属硬掩模层的侧壁的垂直分布可以有利地用于减少转印到下层中的图案与形成在金属硬掩模层上的图案之间的蚀刻偏压中的图案因子依赖性。 此外，灰化化学可以用于增强在金属材料层的垂直部分中的桁条的去除。

公开(公告)号：US09111801B2

公开(公告)日：2015-08-18

申请号：US13856985

申请日：2013-04-04

Applicant: STMicroelectronics, Inc.

Inventor： John H. Zhang

IPC: H01L21/04 ,  H01L27/12 ,  H01L29/66 ,  H01L21/84 ,  H01L27/11

CPC classification number: H01L27/1211 ,  H01L21/266 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823828 ,  H01L21/823871 ,  H01L21/845 ,  H01L23/528 ,  H01L27/0924 ,  H01L27/1104 ,  H01L27/1108 ,  H01L27/11213 ,  H01L29/0649 ,  H01L29/161 ,  H01L29/66795 ,  H01L29/7831 ,  H01L29/7838 ,  H01L29/7849 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Integrated circuit devices and fabrication techniques. A semiconductor device fabrication method may include doping, in a same processing step, first and second portions of a substrate of an integrated circuit. The first portion corresponds to a doped region of a semiconductor device. The second portion corresponds to a via contact. The method may further include, after the doping, forming the gate of the semiconductor device.

Abstract translation: 集成电路器件和制造技术。 半导体器件制造方法可以包括在相同的处理步骤中掺杂集成电路的衬底的第一和第二部分。 第一部分对应于半导体器件的掺杂区域。 第二部分对应于通孔接触。 该方法还可以包括在掺杂之后形成半导体器件的栅极。

公开(公告)号：US20150228781A1

公开(公告)日：2015-08-13

申请号：US14175215

申请日：2014-02-07

Applicant: GLOBALFOUNDRIES Inc. ,  STMICROELECTRONICS, INC.

Inventor： Xiuyu CAI ,  Qing LlU ,  Ruilong XIE

IPC: H01L29/78 ,  H01L29/66

CPC classification number: H01L29/785 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7848

Abstract: A method is for making a semiconductor device. The method may include forming fins above a substrate, each fin having an upper fin portion including a first semiconductor material and a lower fin portion including a dielectric material. The method may include forming recesses into sidewalls of each lower fin portion to expose a lower surface of a respective upper fin portion, and forming a second semiconductor layer surrounding the fins including the exposed lower surfaces of the upper fin portions. The second semiconductor layer may include a second semiconductor material to generate stress in the first semiconductor material.

Abstract translation: 一种制造半导体器件的方法。 该方法可以包括在基板上形成翅片，每个翅片具有包括第一半导体材料的上翅片部分和包括电介质材料的下翅片部分。 该方法可以包括在每个下部翅片部分的侧壁中形成凹部以暴露相应的上部翅片部分的下表面，以及形成包围上翅片部分暴露的下表面的翅片的第二半导体层。 第二半导体层可以包括在第一半导体材料中产生应力的第二半导体材料。

公开(公告)号：US09093556B2

公开(公告)日：2015-07-28

申请号：US13590756

申请日：2012-08-21

Applicant: Qing Liu ,  Prasanna Khare ,  Nicolas Loubet

Inventor： Qing Liu ,  Prasanna Khare ,  Nicolas Loubet

IPC: H01L29/76 ,  H01L21/8238 ,  H01L21/84 ,  H01L29/66 ,  H01L29/78 ,  H01L29/08 ,  H01L21/265 ,  H01L29/417

CPC classification number: H01L27/0886 ,  H01L21/2253 ,  H01L21/26506 ,  H01L21/26513 ,  H01L21/2658 ,  H01L21/26586 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823821 ,  H01L21/845 ,  H01L29/0847 ,  H01L29/41783 ,  H01L29/41791 ,  H01L29/66795 ,  H01L29/66803 ,  H01L29/785

Abstract: A multi-fin FINFET device may include a substrate and a plurality of semiconductor fins extending upwardly from the substrate and being spaced apart along the substrate. Each semiconductor fin may have opposing first and second ends and a medial portion therebetween, and outermost fins of the plurality of semiconductor fins may comprise an epitaxial growth barrier on outside surfaces thereof. The FINFET may further include at least one gate overlying the medial portions of the semiconductor fins, a plurality of raised epitaxial semiconductor source regions between the semiconductor fins adjacent the first ends thereof, and a plurality of raised epitaxial semiconductor drain regions between the semiconductor fins adjacent the second ends thereof.

Abstract translation: 多鳍FINFET器件可以包括衬底和从衬底向上延伸并沿着衬底间隔开的多个半导体鳍片。 每个半导体鳍片可以具有相对的第一和第二端以及它们之间的中间部分，并且多个半导体鳍片的最外面的鳍片可以在其外表面上包括外延生长阻挡层。 FINFET还可以包括覆盖半导体鳍片的中间部分的至少一个栅极，在与其第一端相邻的半导体鳍片之间的多个凸起的外延半导体源极区域和在相邻的半导体鳍片之间的多个凸起的外延半导体漏极区域 其第二端。

公开(公告)号：US09082788B2

公开(公告)日：2015-07-14

申请号：US13906702

申请日：2013-05-31

Applicant: STMICROELECTRONICS, INC. ,  INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Nicolas Loubet ,  Prasanna Khare ,  Huiming Bu

IPC: H01L21/8238 ,  H01L29/66 ,  H01L21/8234 ,  H01L27/12 ,  H01L29/78

CPC classification number: H01L29/66484 ,  H01L21/823481 ,  H01L27/1211 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/6681 ,  H01L29/785

Abstract: A method of making a semiconductor device includes forming an intermediate structure including second semiconductor fin portions above a first semiconductor layer, and top first semiconductor fin portions extending from respective ones of the second semiconductor fin portions. The second semiconductor fin portions are selectively etchable with respect to the top first semiconductor fin portions. A dummy gate is on the intermediate structure. The second semiconductor fin portions are selectively etched to define bottom openings under respective ones of the top first semiconductor fin portions. The bottom openings are filled with a dielectric material.

Abstract translation: 制造半导体器件的方法包括在第一半导体层之上形成包括第二半导体鳍部的中间结构以及从第二半导体鳍部中的相应半导体鳍部延伸的顶部第一半导体鳍部。 第二半导体鳍片部分相对于顶部第一半导体鳍片部分可选择性地蚀刻。 虚拟门在中间结构上。 选择性地蚀刻第二半导体鳍片部分以在顶部第一半导体鳍片部分的相应一个下限定底部开口。 底部开口填充有电介质材料。

公开(公告)号：US20150115370A1

公开(公告)日：2015-04-30

申请号：US14068340

申请日：2013-10-31

Applicant: GLOBALFOUNDRIES Inc. ,  STMicroelectronics, Inc.

Inventor： Qing LIU ,  Ruilong Xie ,  Hyun-Jin Cho

IPC: H01L27/088 ,  H01L29/161 ,  H01L29/06 ,  H01L21/8234

CPC classification number: H01L27/0886 ,  H01L21/823431 ,  H01L29/0649 ,  H01L29/161 ,  H01L29/66795 ,  H01L29/785

Abstract: A method for making a semiconductor device may include forming a first semiconductor layer on a substrate comprising a first semiconductor material, forming a second semiconductor layer on the first semiconductor layer comprising a second semiconductor material, and forming mask regions on the second semiconductor layer and etching through the first and second semiconductor layers to define a plurality of spaced apart pillars on the substrate. The method may further include forming an oxide layer laterally surrounding the pillars and mask regions, and removing the mask regions and forming inner spacers on laterally adjacent corresponding oxide layer portions atop each pillar. The method may additionally include etching through the second semiconductor layer between respective inner spacers to define a pair of semiconductor fins of the second semiconductor material from each pillar, and removing the inner spacers and forming an oxide beneath each semiconductor fin.

Abstract translation: 制造半导体器件的方法可以包括在包括第一半导体材料的衬底上形成第一半导体层，在包括第二半导体材料的第一半导体层上形成第二半导体层，以及在第二半导体层上形成掩模区域和蚀刻 通过第一和第二半导体层在衬底上限定多个间隔开的柱。 该方法可以进一步包括在横向围绕柱和掩模区域形成氧化物层，以及去除掩模区域并在横向相邻的每个柱顶上相应的氧化物层部分上形成内部间隔物。 该方法还可以包括通过相应的内部间隔物之间​​的第二半导体层进行蚀刻，以从每个支柱形成第二半导体材料的一对半导体鳍片，以及去除内部间隔物并在每个半导体鳍片之下形成氧化物。

公开(公告)号：US20150108573A1

公开(公告)日：2015-04-23

申请号：US14060874

申请日：2013-10-23

Applicant: GLOBALFOUNDRIES INC. ,  STMicroelectronics, Inc.

Inventor： Qing Liu ,  Xiuyu Cai ,  Ruilong Xie

IPC: H01L21/8234 ,  H01L27/088

CPC classification number: H01L21/823412 ,  H01L21/823431 ,  H01L21/823481 ,  H01L21/823487 ,  H01L27/0886

Abstract: A method for making a semiconductor device may include forming, on a substrate, at least one stack of alternating first and second semiconductor layers. The first semiconductor layer may comprise a first semiconductor material and the second semiconductor layer may comprise a second semiconductor material. The first semiconductor material may be selectively etchable with respect to the second semiconductor material. The method may further include removing portions of the at least one stack and substrate to define exposed sidewalls thereof, forming respective spacers on the exposed sidewalls, etching recesses through the at least one stack and substrate to define a plurality of spaced apart pillars, selectively etching the first semiconductor material from the plurality of pillars leaving second semiconductor material structures supported at opposing ends by respective spacers, and forming at least one gate adjacent the second semiconductor material structures.

Abstract translation: 制造半导体器件的方法可以包括在衬底上形成交替的第一和第二半导体层的至少一个叠层。 第一半导体层可以包括第一半导体材料，第二半导体层可以包括第二半导体材料。 第一半导体材料可以相对于第二半导体材料可选择性地蚀刻。 该方法还可以包括去除至少一个堆叠和衬底的部分以限定其暴露的侧壁，在暴露的侧壁上形成相应的间隔物，蚀刻通过至少一个堆叠和衬底的凹槽以限定多个间隔开的柱，选择性蚀刻 来自多个柱的第一半导体材料离开第二半导体材料结构，在相对端通过相应的间隔件支撑，并且形成与第二半导体材料结构相邻的至少一个栅极。