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95 条记录 (耗时 0.018 秒)

    Writing to asymmetric memory
    71.
    发明授权
    Writing to asymmetric memory 有权
    写入不对称记忆

    公开(公告)号：US07930513B2

    公开(公告)日：2011-04-19

    申请号：US11935281

    申请日：2007-11-05

    申请人： Vijay Karamcheti ,  Kenneth A. Okin ,  Kumar Ganapathy ,  Ashish Singhai ,  Rajesh Parekh

    发明人： Vijay Karamcheti ,  Kenneth A. Okin ,  Kumar Ganapathy ,  Ashish Singhai ,  Rajesh Parekh

    IPC分类号： G06F12/00

    CPC分类号： G06F12/1009 ,  G06F3/0604 ,  G06F3/0628 ,  G06F3/0638 ,  G06F3/064 ,  G06F3/0646 ,  G06F3/0647 ,  G06F3/068 ,  G06F3/0685 ,  G06F9/5016 ,  G06F12/0207 ,  G06F12/0223 ,  G06F12/0292 ,  G06F12/08 ,  G06F12/10 ,  G06F12/121 ,  G06F12/1475 ,  G06F13/1657 ,  G06F13/1694 ,  G06F2212/205 ,  G06F2212/657 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D10/22

    摘要： A memory controller writes to a virtual address associated with data residing within an asymmetric memory component of main memory that is within a computer system and that has a symmetric memory component, while preserving proximate other data residing within the asymmetric memory component. The symmetric memory component within the main memory of the computer system is configured to enable random access write operations in which an address within a block of the symmetric memory component is written without affecting the availability of other addresses within the block of the symmetric memory component during the writing of that address. The asymmetric memory component is configured to enable block write operations in which writing to an address within a region of the asymmetric memory component affects the availability of other addresses within the region of the asymmetric memory component during the block write operations involving the address.

    摘要翻译： 存储器控制器写入与驻留在计算机系统内的主存储器的非对称存储器组件内的数据相关联的虚拟地址，并且具有对称存储器组件，同时保留驻留在非对称存储器组件内的邻近其他数据。 计算机系统的主存储器内的对称存储器组件被配置为实现随机存取写入操作，其中写入对称存储器组件的块内的地址而不影响对称存储器组件的块内的其他地址的可用性 写这个地址。 非对称存储器组件被配置为启用块写入操作，其中对非对称存储器组件的区域内的地址的写入在涉及地址的块写入操作期间影响非对称存储器组件的区域内的其他地址的可用性。

    Managing Memory Systems Containing Components with Asymmetric Characteristics
    73.
    发明申请
    Managing Memory Systems Containing Components with Asymmetric Characteristics 有权
    管理包含不对称特性组件的内存系统

    公开(公告)号：US20090106478A1

    公开(公告)日：2009-04-23

    申请号：US12254779

    申请日：2008-10-20

    申请人： Kenneth A. Okin ,  Vijay Karamcheti

    发明人： Kenneth A. Okin ,  Vijay Karamcheti

    IPC分类号： G06F12/16 ,  G06F12/00 ,  G06F12/06

    CPC分类号： G06F12/02 ,  G06F11/1658 ,  G06F11/20 ,  G06F12/0246 ,  G06F12/06 ,  G06F12/08 ,  G06F12/10 ,  G06F2212/1032 ,  G06F2212/205 ,  G06F2212/7201 ,  G06F2212/7202 ,  G11C16/3418 ,  G11C16/3427

    摘要： A memory controller (MC) is associated with a remapping table to enable access to content in a memory system that includes asymmetric memory. The MC receives a request for a memory read or an Input/Output (I/O) write from a central processing unit (CPU) for a physical address specified by the system's memory management unit (MMU). The CPU uses the MMU to manage memory operations for the CPU, by translating the virtual addresses associated with CPU instructions into physical addresses representing system memory or I/O locations. The MC for asymmetric memories is configured to process the MMU-specified physical addresses as an additional type of virtual addresses, creating a layer of abstraction between the physical address specified by the MMU and the physical memory address with which that address is associated by the MC. The MC shields the CPU from the computational complexities required to implement a memory system with asymmetric components.

    摘要翻译： 存储器控制器（MC）与重映射表相关联，以使得能够访问包括非对称存储器的存储器系统中的内容。 MC从系统的存储器管理单元（MMU）指定的物理地址从中央处理单元（CPU）接收对存储器读取或输入/输出（I / O）写入的请求。 通过将与CPU指令关联的虚拟地址转换为表示系统内存或I / O位置的物理地址，CPU使用MMU来管理CPU的存储器操作。 用于非对称存储器的MC被配置为处理MMU指定的物理地址作为附加类型的虚拟地址，在MMU指定的物理地址与该地址由MC关联的物理存储器地址之间创建一个抽象层 。 MC屏蔽CPU免受实现具有不对称组件的存储系统所需的计算复杂性。

    Using non-volatile memory resources to enable a virtual buffer pool for a database application
    77.
    发明授权
    Using non-volatile memory resources to enable a virtual buffer pool for a database application 有权

    公开(公告)号：US09436597B1

    公开(公告)日：2016-09-06

    申请号：US13932534

    申请日：2013-07-01

    申请人： Virident Systems Inc.

    发明人： Vijay Karamcheti

    IPC分类号： G06F12/14 ,  G06F12/02 ,  G06F12/10 ,  G11C16/10

    CPC分类号： G06F12/0246 ,  G06F12/06 ,  G06F12/109 ,  G06F17/30519 ,  G06F2212/205 ,  G06F2212/7201 ,  G11C16/102

    摘要： A buffer pool for a database application is maintained in a volatile main memory component. A control portion that corresponds to a block of application data residing on a non-volatile, asymmetric memory component and that includes a reference to a location of the block of application data on the non-volatile, asymmetric memory component is added to the buffer pool maintained in the volatile main memory component. The control portion from the buffer pool maintained in the volatile main memory component that corresponds to the block of application data is accessed and the location of the block of application data on the non-volatile, asymmetric memory component is identified. Based on identifying the location of the block of application data on the non-volatile, asymmetric memory component, the database application is enabled to access the block of application data directly from the non-volatile, asymmetric memory component.

    Multi-chip packaged flash memory/support application specific integrated circuit for flash dual inline memory modules
    79.
    发明授权
    Multi-chip packaged flash memory/support application specific integrated circuit for flash dual inline memory modules 有权
    多芯片封装闪存/支持应用专用集成电路，用于闪存双列直插内存模块

    公开(公告)号：US09318156B2

    公开(公告)日：2016-04-19

    申请号：US14016235

    申请日：2013-09-03

    申请人： Ruban Kanapathippillai ,  Kenneth Alan Okin

    发明人： Ruban Kanapathippillai ,  Kenneth Alan Okin

    IPC分类号： G06F1/16 ,  H05K5/00 ,  H05K7/00 ,  G11C5/04 ,  G11C5/14 ,  G11C16/08 ,  H05K1/18

    CPC分类号： G11C16/30 ,  G11C5/04 ,  G11C5/14 ,  G11C16/08 ,  H01R12/725 ,  H05K1/0286 ,  H05K1/181 ,  H05K2201/10159 ,  H05K2201/10212 ,  Y02P70/611 ,  Y10T29/49002 ,  Y10T29/49117 ,  Y10T29/49124 ,  Y10T29/49128 ,  Y10T29/49169

    摘要： In one implementation, flash memory chips are provided with an operating power supply voltage to substantially match a power supply voltage expected at an edge connector of a dual inline memory module. The one or more of the flash memory chips and a memory support application integrated circuit (ASIC) may be mounted together into a multi-chip package for integrated circuits. The one or more flash memory chips and the memory support ASIC may be electrically coupled together by routing one or more conductors between each in the multi-chip package. The multi-chip package may be mounted onto a printed circuit board (PCB) of a flash memory DIMM to reduce the number of packages mounted thereto and reduce the height of the flash memory DIMM. The number of printed circuit board layers may also be reduced, such as by integrating address functions into the memory support ASIC.

    摘要翻译： 在一个实施方案中，闪存芯片被提供有工作电源电压以基本上匹配预期在双列直插存储器模块的边缘连接器处的电源电压。 一个或多个闪速存储器芯片和存储器支持应用集成电路（ASIC）可以一起安装到用于集成电路的多芯片封装中。 一个或多个闪存芯片和存储器支持ASIC可以通过在多芯片封装中的每一个之间布线一个或多个导体来电耦合在一起。 多芯片封装可以安装在闪存DIMM的印刷电路板（PCB）上，以减少安装在其上的封装件的数量并降低闪存DIMM的高度。 印刷电路板层的数量也可以减少，例如通过将地址功能集成到存储器支持ASIC中。

    Methods for upgrading main memory in computer systems to two-dimensional memory modules and master memory controllers
    80.
    发明授权
    Methods for upgrading main memory in computer systems to two-dimensional memory modules and master memory controllers 有权
    将计算机系统中的主内存升级为二维内存模块和主内存控制器的方法

    公开(公告)号：US09251899B2

    公开(公告)日：2016-02-02

    申请号：US12369733

    申请日：2009-02-11

    申请人： Vijay Karamcheti ,  Kumar Ganapathy

    发明人： Vijay Karamcheti ,  Kumar Ganapathy

    IPC分类号： G06F12/06 ,  G06F7/78 ,  G06F12/02 ,  G11C16/04 ,  G06F17/30

    CPC分类号： G11C16/0408 ,  G06F7/78 ,  G06F12/0207 ,  G06F12/0246 ,  G06F12/0607 ,  G06F17/30477 ,  G06F2212/7201 ,  G06F2212/7208 ,  G11C16/06 ,  Y02D10/13

    摘要： In one embodiment of the invention, a method of upgrading main memory in a computer system is disclosed. The method includes plugging a plurality of two dimensional memory modules into a plurality of memory module sockets and coupling a master memory controller between one or more processors and the plurality of memory modules. Each of the two dimensional memory modules includes memory in a plurality of memory slices and a plurality of slave memory controllers respectively coupled to the memory in the plurality of memory slices. According, the upgrading method further includes buffering and transposing data between a column by column format for the one or more processors and a row by row format for the memory in the plurality of memory slices.

    摘要翻译： 在本发明的一个实施例中，公开了一种在计算机系统中升级主存储器的方法。 该方法包括将多个二维存储器模块插入多个存储器模块插槽中，并将主存储器控制器耦合在一个或多个处理器与多个存储器模块之间。 二维存储器模块中的每一个包括多个存储器片中的存储器和分别耦合到多个存储器片中的存储器的多个从存储器控制器。 根据该升级方法还包括缓冲和转置用于一个或多个处理器的逐列格式的数据以及多个存储器片中的存储器的逐行格式。