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公开(公告)号：US12094519B2
公开(公告)日：2024-09-17
申请号：US17222641
申请日：2021-04-05
Applicant: Changxin Memory Technologies, Inc.
Inventor： Shengcheng Deng
IPC: G11C11/409 , G06F12/06
CPC classification number: G11C11/409 , G06F12/06 , G06F2212/70
Abstract: A data read/write method and device, as well as a dynamic random-access memory (DRAM) having the same are disclosed. The method may include: entering a page read/write mode configured by a reserved bit in a mode register of the DRAM; receiving a page read/write command including a page read/write enable command configured by a reserved bit in a read/write command of the DRAM; and performing a page read/write operation according to the page read/write command. This method may allow a greater amount of data to be handled by each read/write command, thereby reducing the number of required read/write commands. As a result, a higher read/write rate and lower power consumption can be achieved.
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公开(公告)号：US12092654B2
公开(公告)日：2024-09-17
申请号：US17663865
申请日：2022-05-18
Applicant: CHANGXIN MEMORY TECHNOLOGIES, INC.
Inventor： Jinrong Huang
CPC classification number: G01R1/0425 , G01R1/0416 , G01R31/2884 , G01R31/2893 , G01R31/2896
Abstract: The present disclosure discloses an assembly for carrying a chip, and a device and a method for testing a chip. The assembly for carrying a chip is configured to fasten chips of different sizes, and includes a rotatable vertical rod, a cross beam, a first sidewall, and a second sidewall. The rotatable vertical rod is provided with a gear that surrounds the rotatable vertical rod with gear teeth. The cross beam is internally provided with a first through hole and a first chute. A top of the first sidewall is connected to a first connecting rod located in the first chute. A top of the second sidewall is connected to a second connecting rod located in the first chute. A side surface of the first connecting rod is provided with a plurality of first tooth grooves arranged linearly.
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公开(公告)号：US12089401B2
公开(公告)日：2024-09-10
申请号：US17575876
申请日：2022-01-14
Applicant: CHANGXIN MEMORY TECHNOLOGIES, INC.
Inventor： Jingwen Lu
IPC: H10B12/00 , H01L21/768
CPC classification number: H10B12/482 , H01L21/76811 , H10B12/03 , H10B12/30
Abstract: A preparation method of a semiconductor structure includes: providing a base; forming several bit lines arranged in parallel and at intervals on the base, which extend in a first direction; forming capacitor contact material layers between adjacent bit lines, upper surfaces of which are lower than upper surfaces of the bit lines; forming filling medium layers on the capacitor contact material layers; forming several first mask patterns arranged in parallel and at intervals on the filling medium layers and the bit lines, which extend in a second direction that intersects with the first direction; patterning the filling medium layers based on the first mask patterns to form several grooves in the filling medium layers; forming second mask patterns in the grooves; and patterning the capacitor contact material layers based on the second mask patterns to form several cylindrical capacitor contact structures arranged in parallel and at intervals.
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公开(公告)号：US12089400B2
公开(公告)日：2024-09-10
申请号：US17452272
申请日：2021-10-26
Applicant: CHANGXIN MEMORY TECHNOLOGIES, INC.
Inventor： Minki Hong
CPC classification number: H10B12/482 , H01L28/60 , H01L29/66666 , H01L29/7827 , H10B12/038
Abstract: The present disclosure provides a method for forming a semiconductor structure and a semiconductor structure. The method for forming a semiconductor structure includes: providing a substrate, and forming discrete bit line structures on the substrate; forming a first sacrificial layer on the surface of the substrate on the bottoms of gaps of the bit line structures; forming a second sacrificial layer filling the gaps of the discrete bit line structures; patterning the second sacrificial layer and the first sacrificial layer to form openings, the formed openings and the remaining of the second sacrificial layer being arranged alternately in an extension direction of the bit line structures; forming a dielectric layer filling the openings; and, removing the remaining of the first sacrificial layer and the remaining of the second sacrificial layer to form capacitor contact holes, the formed capacitor contact holes and the dielectric layer being arranged alternately.
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公开(公告)号：US12088091B2
公开(公告)日：2024-09-10
申请号：US17810682
申请日：2022-07-05
Applicant: CHANGXIN MEMORY TECHNOLOGIES, INC.
CPC classification number: H02H9/046 , H02H1/0007
Abstract: The present disclosure provides an electrostatic discharge (ESD) protection circuit for a chip, including: a monitoring unit, configured to generate a trigger signal when there is an ESD pulse on a power supply pad; a plurality of controllable drive units, connected to the monitoring unit, and each of the controllable drive units being configured to switch an operating state under a control of a control signal, wherein the operating state includes an output state, and the output state refers to generating a drive signal according to the trigger signal; and a discharge transistor, connected to the plurality of controllable drive units, and configured to be turned on under a drive of the drive signal so as to discharge an electrostatic charge to the ground pad.
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Patent Agency Ranking
76.发明授权公开(公告)号：US12082419B2
公开(公告)日：2024-09-03
申请号：US17444785
申请日：2021-08-10
Applicant: CHANGXIN MEMORY TECHNOLOGIES, INC.
Inventor： Yiming Zhu , Erxuan Ping
Abstract: A method for forming the semiconductor structure includes: providing a substrate, forming a sacrificial layer and an active layer on the sacrificial layer on the substrate; etching the active layer and the sacrificial layer to form active lines extending along a first direction; forming a first isolation layer that fills a spacing between the active lines; etching ends of the active lines to form openings, and exposing the sacrificial layer on side walls of the openings; removing the sacrificial layer along the openings, and forming gap between a bottom of the active lines and the substrate; and filling the gaps with a conductive material to form bit lines extending along the first direction.
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公开(公告)号：US12082393B2
公开(公告)日：2024-09-03
申请号：US17457819
申请日：2021-12-06
Applicant: CHANGXIN MEMORY TECHNOLOGIES, INC.
Inventor： Qiang Wan , Jun Xia , Kangshu Zhan , Sen Li , Tao Liu , Penghui Xu
IPC: H01L27/108 , H10B12/00
Abstract: A method for manufacturing a memory and a memory is provided. The method for manufacturing a memory includes: providing a substrate; stacking an electrode support structure, a protective layer and a first mask layer in sequence on the substrate; patterning the first mask layer on an array region, and etching the protective layer, the electrode support structure and the substrate by using the patterned first mask layer as a mask, to form capacitor holes penetrating the protective layer and the electrode support structure and extending into the substrate; removing the first mask layer; and forming a first electrode layer on side walls and bottom walls of the capacitor holes, a top surface of the first electrode layer being flush with a top surface of the electrode support structure.
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公开(公告)号：US12080340B2
公开(公告)日：2024-09-03
申请号：US17737109
申请日：2022-05-05
Applicant: CHANGXIN MEMORY TECHNOLOGIES, INC.
Inventor： Sungsoo Chi , Shuyan Jin , Fengqin Zhang
IPC: G11C11/4096 , G11C11/4091 , G11C11/4094
CPC classification number: G11C11/4096 , G11C11/4091 , G11C11/4094
Abstract: A control circuit, a method for reading and writing and a memory are provided. The control circuit includes a pre-charge circuit, an amplification circuit and an equalization circuit. The pre-charge circuit is directly electrically connected to at least one of a bit line or a complementary bit line. The amplification circuit has a first node and a second node. The equalization circuit is connected between the first node and the bit line and between the second node and the complementary bit line.
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公开(公告)号：US12080335B2
公开(公告)日：2024-09-03
申请号：US17934185
申请日：2022-09-21
Applicant: CHANGXIN MEMORY TECHNOLOGIES, INC.
Inventor： Zequn Huang
IPC: G11C11/4076 , H03K3/037 , H03K5/135 , H03K19/20
CPC classification number: G11C11/4076 , H03K3/037 , H03K5/135 , H03K19/20
Abstract: A signal sampling circuit includes the following: a signal input circuit, configured to determine a to-be-processed instruction signal and a to-be-processed chip select signal; a first instruction sampling circuit, configured to perform two-stage sampling and logic operation processing on the to-be-processed chip select signal according to a first clock signal to obtain a first chip select clock signal; a second instruction sampling circuit, configured to perform two-stage sampling and logic operation processing on the to-be-processed chip select signal according to the first clock signal to obtain a second chip select clock signal; and an instruction decoding circuit, configured to perform decoding and sampling processing on the to-be-processed instruction signal according to be to-be-processed chip select signal and one of the first chip select clock signal and the second chip select clock signal to obtain a target instruction signal.
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80.发明授权公开(公告)号：US12074075B2
公开(公告)日：2024-08-27
申请号：US17447410
申请日：2021-09-10
Applicant: CHANGXIN MEMORY TECHNOLOGIES, INC.
Inventor： Yukun Li
CPC classification number: H01L22/20 , G06F16/9024 , G06F17/15 , G06F17/18 , G06F18/2193 , G06Q10/04 , H01L22/12 , H01L22/14
Abstract: A data analysis method includes: a target yield problem stacked graph corresponding to a wafer list is obtained, and measurement data stacked graphs of the wafer list under different types of tests are obtained; graph matching is performed on the target yield problem stacked graph and each of the measurement data stacked graphs to obtain matching degree data corresponding to the target yield problem stacked graph and each of the measurement data stacked graphs; correlation data corresponding to each of the measurement data stacked graphs and the target yield problem stacked graph is calculated; and weighted calculation is performed on the matching degree data and the correlation data, and a target measurement parameter causing a target yield problem is determined according to a result of the weighted calculation.
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