公开(公告)号：US06734518B2

公开(公告)日：2004-05-11

申请号：US09924759

申请日：2001-08-08

申请人： Zhiping Yin ,  Gurtej Singh Sandhu

发明人： Zhiping Yin ,  Gurtej Singh Sandhu

IPC分类号： H01L310232

CPC分类号： H01L21/3105 ,  G03F7/091 ,  H01L21/0276 ,  H01L21/3145 ,  H01L21/32139

摘要： The present invention comprises a method for preventing particle formation in a substrate overlying a DARC coating. The method comprises providing a semiconductor construct. A DARC coating is deposited on the construct with a plasma that comprises a silicon-based compound and N2O. The DARC coating is exposed to an atmosphere that effectively prevents a formation of defects in the substrate layer. The exposed DARC coating is overlayed with the substrate.

摘要翻译： 本发明包括防止在覆盖DARC涂层的基板中形成粒子的方法。 该方法包括提供半导体构造。 使用包含硅基化合物和N 2 O的等离子体在构建体上沉积DARC涂层。 DARC涂层暴露于有效防止在基底层中形成缺陷的气氛。 暴露的DARC涂层与基材重叠。

公开(公告)号：US06677640B1

公开(公告)日：2004-01-13

申请号：US09516681

申请日：2000-03-01

申请人： Sukesh Sandhu ,  Dan Gealy ,  Gurtej Singh Sandhu

发明人： Sukesh Sandhu ,  Dan Gealy ,  Gurtej Singh Sandhu

IPC分类号： H01L29792

CPC分类号： H01L21/28273 ,  H01L29/42324 ,  H01L29/513 ,  H01L29/7881

摘要： A dielectric sandwich for use in a memory device is disclosed. The dielectric sandwich is thin and has at least one high permittivity layer having a thickness of between 140 and 240 angstroms. The dielectric sandwich also has at least one oxide layer formed at a temperature above the crystallization temperature of the high permittivity layer. In a flash memory cell the dielectric sandwich is located between the control gate and the floating gate and provides tight coupling between the control gate and the floating gate.

摘要翻译： 公开了一种用于存储器件的电介质夹层。 电介质夹心薄，并且具有至少一个厚介于140和240埃之间的高介电常数层。 电介质夹层物还具有在高介电常数层的结晶温度以上的温度下形成的至少一个氧化物层。 在闪存单元中，电介质夹层位于控制栅极和浮置栅极之间，并且在控制栅极和浮动栅极之间提供紧密耦合。

公开(公告)号：US06472756B2

公开(公告)日：2002-10-29

申请号：US09789999

申请日：2001-02-21

申请人： Trung T. Doan ,  Gurtej Singh Sandhu ,  Kirk Prall ,  Sujit Sharan

发明人： Trung T. Doan ,  Gurtej Singh Sandhu ,  Kirk Prall ,  Sujit Sharan

IPC分类号： H01L214763

CPC分类号： H01L21/76843 ,  C23C16/02 ,  C23C16/0236 ,  C23C16/42 ,  H01L21/28518 ,  H01L21/28556 ,  H01L21/76855

摘要： A method is provided for forming a contact in an integrated circuit by chemical vapor deposition (CVD). In one embodiment, a titanium precursor and a silicon precursor are contacted in the presence of hydrogen, to form titanium silicide. In another embodiment, a titanium precursor contacts silicon to form to form titanium silicide.

摘要翻译： 提供了一种通过化学气相沉积（CVD）在集成电路中形成接触的方法。 在一个实施方案中，在氢的存在下使钛前体和硅前体接触以形成硅化钛。 在另一个实施方案中，钛前体与硅接触以形成硅化钛。

公开(公告)号：US06433434B1

公开(公告)日：2002-08-13

申请号：US09389562

申请日：1999-09-03

申请人： Gurtej Singh Sandhu ,  Donald L. Westmoreland

发明人： Gurtej Singh Sandhu ,  Donald L. Westmoreland

IPC分类号： H01L2348

CPC分类号： H01L21/76855 ,  C23C16/0281 ,  C23C16/06 ,  H01L21/28568 ,  H01L21/76843 ,  H01L21/76858 ,  H01L21/76876

摘要： Structures within semiconductor devices having a titanium alloy layer are provided. The titanium alloy layer is formed through chemical vapor deposition by combining a first precursor with a reducing agent to form a seed layer, and by combining a second precursor with the seed layer to form the titanium alloy layer. Structures are described having a titanium alloy layer on sidewalls and an exposed base layer of a contact hole. Structures are further described having a titanium alloy layer on sidewalls of a contact hole and a titanium silicide layer on an exposed base layer of the contact hole. The structures are useful as device contacts to active areas of a semiconductor device, and as interlevel vias within semiconductor integrated circuits.

摘要翻译： 提供具有钛合金层的半导体器件内的结构。 通过将第一前体与还原剂组合形成种子层，并且通过将第二前体与种子层组合以形成钛合金层，通过化学气相沉积形成钛合金层。 描述了在侧壁上具有钛合金层和接触孔的暴露的基底层的结构。 进一步描述在接触孔的暴露的基底层上在接触孔的侧壁上具有钛合金层和硅化钛层的结构。 该结构可用作半导体器件的有源区域的器件触点，以及半导体集成电路内的层间通孔。

公开(公告)号：US06312486B1

公开(公告)日：2001-11-06

申请号：US09605164

申请日：2000-06-27

申请人： Gurtej Singh Sandhu ,  Donald Westmoreland ,  Daniel Koos

发明人： Gurtej Singh Sandhu ,  Donald Westmoreland ,  Daniel Koos

IPC分类号： B08B700

CPC分类号： H01L21/02024 ,  C09G1/02 ,  H01L21/31053

摘要： A slurry composition enhances the removal of polish-resistant surface moieties from the surface of a semiconductor wafer during chemical-mechanical polishing. The slurry composition is a mixture including a solvent, a plurality of abrasive particles, and a chelating agent. The abrasive particles abrade the surface of the wafer to remove surface moieties and underlying material. The chelating agent is selected to react with polish-resistant surface moieties on the surface of the wafer surface, to thereby render the surface moieties easier to remove from the surface layer with substantially non-aggressive chemical-mechanical polishing techniques. In operation, the surface moieties and the underlying bulk material are removed by a combination of the chemical effects of the chelating agent and the mechanical effects of the abrasive particles.

摘要翻译： 在化学机械抛光期间，浆料组合物增强了从半导体晶片的表面去除耐抛光表面部分。 浆料组合物是包括溶剂，多个磨料颗粒和螯合剂的混合物。 研磨颗粒磨损晶片的表面以去除表面部分和下面的材料。 螯合剂被选择为与晶片表面表面上的抗抛光表面部分反应，从而使得表面部分更容易用基本上非侵蚀性的化学机械抛光技术从表面层去除。 在操作中，通过螯合剂的化学作用和磨料颗粒的机械效应的组合来去除表面部分和下面的体积材料。

公开(公告)号：US06249019B1

公开(公告)日：2001-06-19

申请号：US09310624

申请日：1999-05-12

申请人： Gurtej Singh Sandhu ,  Randhir P. S. Thakur

发明人： Gurtej Singh Sandhu ,  Randhir P. S. Thakur

IPC分类号： H01L2976

CPC分类号： H01L27/10852 ,  H01L28/82 ,  H01L28/84 ,  H01L28/90

摘要： A capacitor electrode for use on an integrated circuit is formed of a layer of polysilicon having first and second opposing surfaces separated by a thickness of between 250 and 1000 angstroms. Both of the first and second opposing surfaces have a roughened outer texture.

摘要翻译： 用于集成电路的电容器电极由多晶硅层形成，该多晶硅层的第一和第二相对表面分隔了250至1000埃的厚度。 第一和第二相对表面都具有粗糙的外部纹理。

公开(公告)号：US06171943B2

公开(公告)日：2001-01-09

申请号：US09377273

申请日：1999-08-19

申请人： Trung T. Doan ,  Gurtej Singh Sandhu ,  Kirk Prall ,  Sujit Sharan

发明人： Trung T. Doan ,  Gurtej Singh Sandhu ,  Kirk Prall ,  Sujit Sharan

IPC分类号： H01L214763

CPC分类号： H01L21/76843 ,  C23C16/02 ,  C23C16/0236 ,  C23C16/42 ,  H01L21/28518 ,  H01L21/28556 ,  H01L21/76855

摘要： A method is provided for forming a contact in an integrated circuit by chemical vapor deposition (CVD). In one embodiment, a titanium precursor and a silicon precursor are contacted in the presence of hydrogen, to form titanium silicide. In another embodiment, a titanium precursor contacts silicon to form to form titanium silicide.

摘要翻译： 提供了一种通过化学气相沉积（CVD）在集成电路中形成接触的方法。 在一个实施方案中，在氢的存在下使钛前体和硅前体接触以形成硅化钛。 在另一个实施方案中，钛前体与硅接触以形成硅化钛。

公开(公告)号：US6144095A

公开(公告)日：2000-11-07

申请号：US912051

申请日：1997-08-18

申请人： Gurtej Singh Sandhu ,  Chris Chang Yu

发明人： Gurtej Singh Sandhu ,  Chris Chang Yu

IPC分类号： H01L21/288 ,  H01L21/768 ,  H01L23/48

CPC分类号： H01L21/76873 ,  H01L21/2885 ,  H01L21/76838 ,  H01L21/76841 ,  H01L21/76843 ,  H01L21/76865 ,  H01L21/76877 ,  H01L21/76879 ,  H01L2224/05572 ,  H01L2924/0002

摘要： An integrated circuit includes a metallization layer (30). A first layer (14) is formed outwardly from a semiconductor substrate (10). Contact vias (16) are formed through the first layer (14) to the semiconductor substrate (10). A second layer (20) is formed outwardly from the first layer (14). Portions of the second layer (20) are selectively removed such that the remaining portion of the second layer (20) defines the layout of the metallization layer (30) and the contact vias (16). The first and second layers (14) and (20) are electroplated by applying a bi-polar modulated voltage having a positive duty cycle and a negative duty cycle to the layers in a solution containing metal ions. The voltage and surface potentials are selected such that the metal ions are deposited on the remaining portions of the second layer (20). Further, metal ions deposited on the first layer (14) during a positive duty cycle are removed from the first layer (14) during a negative duty cycle. Finally, exposed portions of the firs layer (14) are selectively removed.

摘要翻译： 集成电路包括金属化层（30）。 第一层（14）从半导体衬底（10）向外形成。 接触通孔（16）通过第一层（14）形成到半导体衬底（10）。 第二层（20）从第一层（14）向外形成。 选择性地去除第二层（20）的部分，使得第二层（20）的剩余部分限定金属化层（30）和接触通孔（16）的布局。 通过在含有金属离子的溶液中的层上施加具有正占空比和负占空比的双极调制电压来对第一和第二层（14）和（20）进行电镀。 选择电压和表面电位使得金属离子沉积在第二层（20）的剩余部分上。 此外，在负占空比期间，在正占空比期间沉积在第一层（14）上的金属离子从第一层（14）去除。 最后，选择性地去除第一层（14）的暴露部分。

公开(公告)号：US6124607A

公开(公告)日：2000-09-26

申请号：US96006

申请日：1998-06-11

申请人： Gurtej Singh Sandhu ,  Randhir P. S. Thakur

发明人： Gurtej Singh Sandhu ,  Randhir P. S. Thakur

IPC分类号： H01L21/02 ,  H01L27/108 ,  H01L29/76 ,  H01L29/94

CPC分类号： H01L28/82 ,  H01L28/84 ,  H01L28/87 ,  Y10S438/964

摘要： A method and apparatus for enhanced capacitance per unit area electrodes is utilized in semiconductor memory devices. The capacitance is enhanced by roughening the surface of the bottom electrode in such devices. In one embodiment of the invention, surface roughness is achieved on a polysilicon bottom capacitor electrode by depositing doped polysilicon on the outside surfaces of a bottom capacitor electrode and vacuum annealing. In another embodiment of the invention, surface roughness is achieved by depositing a GeO.sub.2 -embedded GeBPSG layer on a substrate, annealing, selectively etching to remove GeO.sub.2, forming a container, and depositing a blanket rough polysilicon layer over the GeBPSG layer to replicate the underlying surface roughness.

摘要翻译： 在半导体存储器件中使用了用于增强每单位面积电极的电容的方法和装置。 通过在这样的器件中使底部电极的表面粗糙化来增强电容。 在本发明的一个实施例中，通过在底部电容器电极的外表面上沉积掺杂多晶硅和真空退火，在多晶硅底部电容器电极上实现表面粗糙度。 在本发明的另一个实施方案中，通过在衬底上沉积GeO 2嵌入的GeBPSG层，退火，选择性蚀刻去除GeO 2，形成容器，以及在GeBPSG层上沉积覆盖的粗糙多晶硅层，以复制底层 表面粗糙度。

公开(公告)号：US6108092A

公开(公告)日：2000-08-22

申请号：US328034

申请日：1999-06-08

申请人： Gurtej Singh Sandhu

发明人： Gurtej Singh Sandhu

IPC分类号： G01B11/06 ,  B24B37/04 ,  B24B49/04 ,  B24B49/12 ,  H01L21/304 ,  H01L21/306 ,  H01L21/66

CPC分类号： B24B37/013 ,  B24B37/04 ,  B24B49/04 ,  B24B49/12 ,  G01B11/0683 ,  H01L22/26 ,  H01L2924/0002

摘要： A method and apparatus for detecting the endpoint of CMP processing on semiconductor wafer in which a lower layer of material with a first reflectivity is positioned under an upper layer of material with a second reflectivity. Initially an endpoint site is selected on the wafer in a critical area where a boundary between the upper and lower layers defines the desired endpoint of the CMP process. The critical area on the wafer is generally determined by analyzing in the circuit design and the polishing characteristics of previously polished test wafers to denote the last points on the wafer from which the upper layer is desirably removed by CMP processing. After an endpoint site is selected, a light beam impinges the polished surface of the wafer and reflects off of the surface of the wafer to a photo-sensor. The photosensor senses the actual intensity of the reflected light beam. The actual intensity of the reflected light beam is compared with an expected intensity to determine whether the upper layer has been adequately removed from the endpoint site. The actual intensity is preferably compared with an expected intensity for light reflected from one of the upper or lower layers, and the endpoint is preferably detected when the actual intensity of the reflected light beam is either substantially the same as the expected intensity for light reflected from the lower layer or substantially different from the expected intensity for light reflected from the upper layer.

摘要翻译： 一种用于检测半导体晶片上的CMP处理的终点的方法和装置，其中具有第一反射率的下层材料位于具有第二反射率的上层材料的下方。 最初，在晶圆上选择端点位置，其中上层和下层之间的边界限定CMP工艺的期望端点。 晶片上的关键区域通常通过在电路设计中分析和先前抛光的测试晶片的抛光特性来确定，以表示通过CMP处理希望从其上去除上层的晶片上的最后点。 在选择端点位置之后，光束照射晶片的抛光表面并从晶片的表面反射到光电传感器。 光传感器感测反射光束的实际强度。 将反射光束的实际强度与预期强度进行比较，以确定上层是否已经从端点位点被适当地去除。 优选地将实际强度与从上层或下层中的一层反射的光的预期强度进行比较，并且优选地，当反射光束的实际强度基本上与从 下层或与从上层反射的光的预期强度基本上不同。