公开(公告)号：US20100283518A1

公开(公告)日：2010-11-11

申请号：US12493831

申请日：2009-06-29

Applicant: Seung Joon AHN ,  Jong Chern LEE

Inventor： Seung Joon AHN ,  Jong Chern LEE

IPC: H03L7/06 ,  H03L7/00

CPC classification number: H03L7/0814 ,  H03K5/131 ,  H03K2005/00234

Abstract: A delay apparatus of a semiconductor integrated circuit includes a control signal generating unit configured to generate a block control signal and a unit control signal in response to a delay control signal; a plurality of delay blocks, connected in series to each other, and configured to generate a delay clock signal by delaying an input clock signal, wherein each of the delay blocks includes a predetermined number of unit delayers, and the plurality of the delay blocks are configured to be selectively activated in response to the block control signal; and a minute delay unit including a predetermined number of unit delayers and configured to generate an output clock signal by delaying the delay clock signal by adjusting an activation number of the provided unit delayers in response to the unit control signal.

Abstract translation: 半导体集成电路的延迟装置包括：控制信号生成单元，被配置为响应延迟控制信号产生块控制信号和单元控制信号; 多个延迟块，其彼此串联连接，并且被配置为通过延迟输入时钟信号来产生延迟时钟信号，其中每个延迟块包括预定数量的单位延迟器，并且所述多个延迟块是 被配置为响应于所述块控制信号被选择性地激活; 以及包括预定数量的单位延迟器的分钟延迟单元，并且被配置为通过响应于单元控制信号调整所提供的单位延迟器的激活数来延迟延迟时钟信号来产生输出时钟信号。

公开(公告)号：US20090146697A1

公开(公告)日：2009-06-11

申请号：US12137127

申请日：2008-06-11

Applicant: Jong Chern LEE

Inventor： Jong Chern LEE

IPC: H03K3/00

CPC classification number: H03K19/01707 ,  H03K19/01721 ,  H03K19/018528

Abstract: The buffer circuit includes a differential amplifier differentially amplifying a reference node corresponding to a reference voltage and an input node corresponding to the input signal by sensing a potential difference of the reference voltage and the input signal. A coupling unit couples the input signal to the reference node, making it possible to improve the operating speed of the buffer circuit and operate normally when a level of the input signal or the reference voltage becomes low.

Abstract translation: 缓冲电路包括差分放大器，通过感测参考电压和输入信号的电位差，差分放大对应于参考电压的参考节点和对应于输入信号的输入节点。 耦合单元将输入信号耦合到参考节点，使得当输入信号或参考电压的电平变低时，可以提高缓冲电路的工作速度并正常工作。

公开(公告)号：US20080001582A1

公开(公告)日：2008-01-03

申请号：US11717662

申请日：2007-03-14

Applicant: Jong-Chern Lee ,  Sun-Hye Shin

Inventor： Jong-Chern Lee ,  Sun-Hye Shin

IPC: G05F1/10

CPC classification number: G05F1/465

Abstract: An internal voltage generator of a semiconductor memory device is capable of changing driving abilities between standby and active modes, to respond faster in the active mode and prevent a leakage current in the standby mode. The internal voltage generator of a semiconductor memory device comprises a driving controller for generating drive control signals having information about standby and active modes, a first voltage generator enabled by the drive control signals for comparing an internal voltage with a reference voltage in the standby and active modes, a first driver for generating the internal voltage according to a comparison performed by the first voltage generator, a second voltage generator enabled by the drive control signal for comparing the internal voltage with the reference voltage in the active mode, and a second driver for generating the internal voltage according to a comparison performed by the second voltage generator.

Abstract translation: 半导体存储器件的内部电压发生器能够改变待机模式和有源模式之间的驱动能力，以便在待机模式下更快地响应并防止在待机模式下的漏电流。 半导体存储器件的内部电压发生器包括用于产生具有关于待机和有功模式的信息的驱动控制信号的驱动控制器，通过用于将内部电压与待机和有效模式下的参考电压进行比较的驱动控制信号使能的第一电压发生器 模式，用于根据由第一电压发生器进行的比较产生内部电压的第一驱动器，通过用于将内部电压与活动模式中的参考电压进行比较的驱动控制信号使能的第二电压发生器和用于 根据由第二电压发生器执行的比较产生内部电压。

公开(公告)号：US20070263465A1

公开(公告)日：2007-11-15

申请号：US11641857

申请日：2006-12-20

Applicant: Jong Chern Lee

Inventor： Jong Chern Lee

IPC: G11C7/00

CPC classification number: G11C7/1048 ,  G11C7/02

Abstract: Disclosed is a precharge circuit of a semiconductor apparatus. The precharge circuit of a semiconductor memory apparatus includes a first precharge unit and a second precharge unit. The first precharge unit applies a first core voltage to a pair of local input/output lines, in response to a first precharge signal, to precharge the pair of local input/output lines. The second precharge unit applies a clamp voltage, which is generated using a first supply voltage, to the pair of local input/output lines, in response to the first precharge signal, to precharge the pair of local input/output lines.

Abstract translation: 公开了一种半导体装置的预充电电路。 半导体存储器装置的预充电电路包括第一预充电单元和第二预充电单元。 第一预充电单元响应于第一预充电信号向一对本地输入/输出线施加第一芯电压，以对该对本地输入/输出线进行预充电。 第二预充电单元响应于第一预充电信号，向一对本地输入/输出线施加使用第一电源电压产生的钳位电压，以对该对本地输入/输出线进行预充电。

公开(公告)号：US07157893B2

公开(公告)日：2007-01-02

申请号：US10878568

申请日：2004-06-29

Applicant: Jong-Chern Lee

Inventor： Jong-Chern Lee

IPC: G05F3/16

CPC classification number: G05F3/245 ,  Y10S323/907

Abstract: There is provided a reference voltage generator that generates a constant reference voltage regardless of a change in temperature. The reference voltage generator includes a temperature-compensated current generating part for reducing a supply current provided to an output terminal in response to an increase of temperature, and a diode for receiving the supply current through the output terminal.

Abstract translation: 提供了参考电压发生器，其产生恒定的参考电压，而与温度的变化无关。 参考电压发生器包括温度补偿电流产生部件，用于响应于温度升高而减小提供给输出端子的电源电流;以及二极管，用于接收通过输出端子的电源电流。

公开(公告)号：US09928205B2

公开(公告)日：2018-03-27

申请号：US13162702

申请日：2011-06-17

Applicant: Dae Suk Kim ,  Jong Chern Lee ,  Sang Jin Byeon

Inventor： Dae Suk Kim ,  Jong Chern Lee ,  Sang Jin Byeon

IPC: G06F13/42 ,  G11C16/20 ,  G11C5/02 ,  G11C5/04 ,  G11C5/06 ,  H01L25/065

CPC classification number: G06F13/4247

Abstract: A semiconductor apparatus may include a master chip, first to nth slave chips, first to nth slave chip ID generating units, and a master chip ID generating unit. The first to nth slave chip ID generating units are disposed respectively in the first to nth slave chips and connected in series to each other. Each of the first to nth slave chip ID generating units is configured to add a predetermined code value to an mth operation code to generate an (m+1)th operation code. The master chip ID generating unit is disposed in the master chip to generate a variable first operation code in response to a select signal. Here, ‘n’ is an integer that is equal to or greater than 2, and ‘m’ is an integer that is equal to or greater than 1 and equal to or smaller than ‘n’.

公开(公告)号：US08823181B2

公开(公告)日：2014-09-02

申请号：US13604449

申请日：2012-09-05

Applicant: Chul Kim ,  Jong Chern Lee

Inventor： Chul Kim ,  Jong Chern Lee

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L23/04 ,  H01L23/02 ,  H01L23/12 ,  H01L25/065 ,  H01L23/498 ,  H01L23/00 ,  H01L21/768

CPC classification number: H01L21/76885 ,  H01L21/76877 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/49811 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/13 ,  H01L24/16 ,  H01L25/0657 ,  H01L2224/0361 ,  H01L2224/0401 ,  H01L2224/05009 ,  H01L2224/05556 ,  H01L2224/05557 ,  H01L2224/05568 ,  H01L2224/0557 ,  H01L2224/05647 ,  H01L2224/06181 ,  H01L2224/13025 ,  H01L2224/131 ,  H01L2224/16013 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/00014 ,  H01L2924/10253 ,  H01L2924/37001 ,  H01L2924/00012 ,  H01L2924/014 ,  H01L2224/05552

Abstract: In a semiconductor apparatus, a plurality of semiconductor chips including through-silicon vias are stacked in a vertical direction, wherein the through-silicon via formed in each semiconductor chip protrudes beyond heights of each semiconductor chip.

Abstract translation: 在半导体装置中，包括贯通硅通孔的多个半导体芯片在垂直方向堆叠，其中形成在每个半导体芯片中的贯通硅通孔突出超过每个半导体芯片的高度。

公开(公告)号：US08581369B2

公开(公告)日：2013-11-12

申请号：US13620404

申请日：2012-09-14

Applicant: Jun-Gi Choi ,  Jong-Chern Lee

Inventor： Jun-Gi Choi ,  Jong-Chern Lee

IPC: H01L23/544

CPC classification number: H01L22/32 ,  H01L22/34 ,  H01L23/585 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor wafer includes at least one chip formed on a substrate, and a scribe line region surrounding the chip. The chip includes a device formation region, and a chip boundary region surrounding the device formation region and formed between the device formation region and the scribe line region. The chip boundary region includes a guard ring structure which physically separates the device formation region from the scribe line region. The guard ring structure includes a signal transfer element which transfers an electric signal between the device formation region and the scribe line region.

Abstract translation: 半导体晶片包括形成在基板上的至少一个芯片和围绕芯片的划线区域。 芯片包括器件形成区域和围绕器件形成区域并形成在器件形成区域和划线区域之间的芯片边界区域。 芯片边界区域包括将器件形成区域与划线区域物理分离的保护环结构。 保护环结构包括在器件形成区域和划线区域之间传送电信号的信号传输元件。

公开(公告)号：US08300486B2

公开(公告)日：2012-10-30

申请号：US12650073

申请日：2009-12-30

Applicant: Je-Yoon Kim ,  Jong-Chern Lee

Inventor： Je-Yoon Kim ,  Jong-Chern Lee

IPC: G11C7/04

CPC classification number: G11C7/04 ,  G11C11/406 ,  G11C11/40626

Abstract: A temperature detection circuit of a semiconductor memory apparatus includes a fixed period oscillator, a temperature variable signal generating unit and a counting unit. The oscillator is configured to generate a fixed period oscillator signal when an enable signal is enabled. The temperature variable signal generating unit is configured to generate a temperature variable signal whose enable interval varies based on temperature variations, when the enable signal is enabled. The counting unit is configured to count the oscillator signal during the enable interval of the temperature variable signal to generate a temperature information signal.

Abstract translation: 半导体存储装置的温度检测电路包括固定周期振荡器，温度可变信号发生单元和计数单元。 振荡器被配置为当启用使能信号时产生固定周期振荡器信号。 温度可变信号发生单元被配置为当使能信号被使能时，产生其使能间隔基于温度变化而变化的温度可变信号。 计数单元被配置为在温度可变信号的使能间隔期间对振荡器信号进行计数，以产生温度信息信号。

公开(公告)号：US08254205B2

公开(公告)日：2012-08-28

申请号：US12493835

申请日：2009-06-29

Applicant: Jong Chern Lee

Inventor： Jong Chern Lee

IPC: G11C19/00 ,  G11C8/00

CPC classification number: G11C8/04 ,  G11C8/18

Abstract: A circuit for shifting an address includes a shift cell block configured to sequentially shift address signals in response to shift control signals and a control cell block configured to generate the shift control signals for activating the shift cell block in a column unit using sequentially shifted read commands or write commands.

Abstract translation: 用于移位地址的电路包括：移位单元块，被配置为响应于移位控制信号顺序地移位地址信号;以及控制单元块，被配置为使用顺序移位的读取命令生成用于以列单元激活移位单元块的移位控制信号 或写命令。