公开(公告)号：US07915642B2

公开(公告)日：2011-03-29

申请号：US12319097

申请日：2008-12-30

Applicant: Ravi Pillarisetty ,  Mantu Hudait ,  Marko Radosavljevic ,  Willy Rachmady ,  Gilbert Dewey ,  Jack Kavalieros

Inventor： Ravi Pillarisetty ,  Mantu Hudait ,  Marko Radosavljevic ,  Willy Rachmady ,  Gilbert Dewey ,  Jack Kavalieros

IPC: H01L29/778

CPC classification number: H01L29/155 ,  H01L21/823807 ,  H01L21/823892 ,  H01L29/0653 ,  H01L29/205 ,  H01L29/207 ,  H01L29/66431 ,  H01L29/66462 ,  H01L29/66795 ,  H01L29/7831

Abstract: Embodiments of an apparatus and methods for providing three-dimensional complementary metal oxide semiconductor devices comprising modulation doped transistors are generally described herein. Other embodiments may be described and claimed.

Abstract translation: 本文通常描述用于提供包括调制掺杂晶体管的三维互补金属氧化物半导体器件的装置和方法的实施例。 可以描述和要求保护其他实施例。

公开(公告)号：US20100289062A1

公开(公告)日：2010-11-18

申请号：US12454354

申请日：2009-05-15

Applicant: Ravi Pillarisetty ,  Mantu Uudait ,  Marko Radosavljevic ,  Gilbert Dewey ,  Jack T. Kavalieros

Inventor： Ravi Pillarisetty ,  Mantu Uudait ,  Marko Radosavljevic ,  Gilbert Dewey ,  Jack T. Kavalieros

IPC: H01L29/20

CPC classification number: H01L29/66522 ,  H01L29/1054 ,  H01L29/122 ,  H01L29/205 ,  H01L29/66477

Abstract: A surface channel transistor is provided in a semiconductive device. The surface channel transistor is either a PMOS or an NMOS device. Epitaxial layers are disposed above the surface channel transistor to cause an increased bandgap phenomenon nearer the surface of the device. A process of forming the surface channel transistor includes grading the epitaxial layers.

Abstract translation: 表面沟道晶体管设置在半导体器件中。 表面沟道晶体管是PMOS或NMOS器件。 外延层设置在表面沟道晶体管的上方，导致更接近器件表面的带隙现象增加。 形成表面沟道晶体管的工艺包括对外延层进行分级。

公开(公告)号：US20100163926A1

公开(公告)日：2010-07-01

申请号：US12345489

申请日：2008-12-29

Applicant: Mantu K. Hudait ,  Ravi Pillarisetty ,  Marko Radosavljevic ,  Gilbert Dewey ,  Jack T. Kavalieros

Inventor： Mantu K. Hudait ,  Ravi Pillarisetty ,  Marko Radosavljevic ,  Gilbert Dewey ,  Jack T. Kavalieros

IPC: H01L29/267 ,  H01L21/336

CPC classification number: H01L29/785 ,  H01L29/1054 ,  H01L29/66795

Abstract: Modulation-doped multi-gate devices are generally described. In one example, an apparatus includes a semiconductor substrate having a surface, one or more buffer films coupled to the surface of the semiconductor substrate, a first barrier film coupled to the one or more buffer films, a multi-gate fin coupled to the first barrier film, the multi-gate fin comprising a source region, a drain region, and a channel region of a multi-gate device wherein the channel region is disposed between the source region and the drain region, a spacer film coupled to the multi-gate fin, and a doped film coupled to the spacer film.

Abstract translation: 通常描述调制掺杂多栅极器件。 在一个示例中，设备包括具有表面的半导体衬底，耦合到半导体衬底的表面的一个或多个缓冲膜，耦合到该一个或多个缓冲膜的第一阻挡膜，耦合到第一 所述多栅极鳍片包括源极区域，漏极区域和多栅极器件的沟道区域，其中所述沟道区域设置在所述源极区域和所述漏极区域之间，间隔膜耦合到所述多栅极器件， 栅极鳍片以及耦合到间隔膜的掺杂膜。

公开(公告)号：US07608883B2

公开(公告)日：2009-10-27

申请号：US12072971

申请日：2008-02-28

Applicant: Marko Radosavljevic ,  Amlan Majumdar ,  Suman Datta ,  Justin Brask ,  Brian Doyle ,  Robert Chau

Inventor： Marko Radosavljevic ,  Amlan Majumdar ,  Suman Datta ,  Justin Brask ,  Brian Doyle ,  Robert Chau

IPC: H01L29/76

CPC classification number: G11C13/025 ,  B82Y10/00 ,  G11C2213/17 ,  H01L29/78696 ,  H01L51/0048 ,  H01L51/0541

Abstract: A transistor is described having a source electrode and a drain electrode. The transistor has at least one semiconducting carbon nanotube that is electrically coupled between the source and drain electrodes. The transistor has a gate electrode and dielectric material containing one or more quantum dots between the carbon nanotube and the gate electrode.

Abstract translation: 描述了具有源电极和漏电极的晶体管。 晶体管具有至少一个电耦合在源极和漏极之间的半导体碳纳米管。 晶体管具有在碳纳米管和栅电极之间含有一个或多个量子点的栅电极和电介质材料。

公开(公告)号：US20090242873A1

公开(公告)日：2009-10-01

申请号：US12058101

申请日：2008-03-28

Applicant: Ravi Pillarisetty ,  Mantu K. Hudait ,  Marko Radosavljevic ,  Gilbert Dewey ,  Titash Rakshit ,  Robert S. Chau

Inventor： Ravi Pillarisetty ,  Mantu K. Hudait ,  Marko Radosavljevic ,  Gilbert Dewey ,  Titash Rakshit ,  Robert S. Chau

IPC: H01L29/12 ,  H01L21/338

CPC classification number: H01L29/7783 ,  H01L29/42316 ,  H01L29/7784

Abstract: Semiconductor heterostructures to reduce short channel effects are generally described. In one example, an apparatus includes a semiconductor substrate, one or more buffer layers coupled to the semiconductor substrate, a first barrier layer coupled to the one or more buffer layers, a back gate layer coupled to the first barrier layer wherein the back gate layer includes a group III-V semiconductor material, a group II-VI semiconductor material, or combinations thereof, the back gate layer having a first bandgap, a second barrier layer coupled to the back gate layer wherein the second barrier layer includes a group III-V semiconductor material, a group II-VI semiconductor material, or combinations thereof, the second barrier layer having a second bandgap that is relatively larger than the first bandgap, and a quantum well channel coupled to the second barrier layer, the quantum well channel having a third bandgap that is relatively smaller than the second bandgap.

Abstract translation: 通常描述用于减少短通道效应的半导体异质结构。 在一个示例中，设备包括半导体衬底，耦合到半导体衬底的一个或多个缓冲层，耦合到一个或多个缓冲层的第一势垒层，耦合到第一阻挡层的背栅层，其中背栅层 包括III-V族半导体材料，II-VI族半导体材料或其组合，所述背栅层具有第一带隙，耦合到所述背栅层的第二阻挡层，其中所述第二阻挡层包括III- V族半导体材料，II-VI族半导体材料或其组合，所述第二阻挡层具有相对大于所述第一带隙的第二带隙，以及耦合到所述第二阻挡层的量子阱沟道，所述量子阱沟道具有 相对小于第二带隙的第三带隙。

公开(公告)号：US20080258207A1

公开(公告)日：2008-10-23

申请号：US11855823

申请日：2007-09-14

Applicant: Marko Radosavljevic ,  Amlan Majumdar ,  Brian S. Doyle ,  Jack Kavalieros ,  Mark L. Doczy ,  Justin K. Brask ,  Uday Shah ,  Suman Datta ,  Robert S. Chau

Inventor： Marko Radosavljevic ,  Amlan Majumdar ,  Brian S. Doyle ,  Jack Kavalieros ,  Mark L. Doczy ,  Justin K. Brask ,  Uday Shah ,  Suman Datta ,  Robert S. Chau

IPC: H01L29/786

CPC classification number: H01L29/785 ,  H01L29/41791 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7851 ,  H01L29/78681 ,  H01L29/78684 ,  H01L2029/7858

Abstract: A contact architecture for nanoscale channel devices having contact structures coupling to and extending between source or drain regions of a device having a plurality of parallel semiconductor bodies. The contact structures being able to contact parallel semiconductor bodies having sub-lithographic pitch.

Abstract translation: 一种用于纳米尺度通道器件的接触结构，其具有耦合到具有多个平行半导体器件的器件的源极或漏极区域之间并具有接触结构的接触结构。 接触结构能够接触具有亚光刻间距的平行半导体本体。

公开(公告)号：US20080203381A1

公开(公告)日：2008-08-28

申请号：US11712191

申请日：2007-02-28

Applicant: Mantu K. Hudait ,  Jack T. Kavalieros ,  Suman Datta ,  Marko Radosavljevic

Inventor： Mantu K. Hudait ,  Jack T. Kavalieros ,  Suman Datta ,  Marko Radosavljevic

IPC: H01L29/06 ,  H01L21/8238

CPC classification number: H01L21/823807 ,  B82Y10/00 ,  H01L21/02381 ,  H01L21/02463 ,  H01L21/02546 ,  H01L21/8252 ,  H01L21/8258 ,  H01L27/0605 ,  H01L29/045 ,  H01L29/0665 ,  H01L29/0673 ,  H01L29/151 ,  H01L29/201 ,  H01L29/207 ,  H01L29/365

Abstract: In one embodiment, the present invention includes a method for forming a logic device, including forming an n-type semiconductor device over a silicon (Si) substrate that includes an indium gallium arsenide (InGaAs)-based stack including a first buffer layer, a second buffer layer formed over the first buffer layer, a first device layer formed over the second buffer layer. Further, the method may include forming a p-type semiconductor device over the Si substrate from the InGaAs-based stack and forming an isolation between the n-type semiconductor device and the p-type semiconductor device. Other embodiments are described and claimed.

Abstract translation: 在一个实施例中，本发明包括一种用于形成逻辑器件的方法，包括在硅（Si）衬底上形成n型半导体器件，该衬底包括基于砷化铟镓（InGaAs）的堆叠，其包括第一缓冲层， 形成在第一缓冲层上的第二缓冲层，形成在第二缓冲层上的第一器件层。 此外，该方法可以包括从基于InGaAs的叠层在Si衬底上形成p型半导体器件，并且在n型半导体器件和p型半导体器件之间形成隔离。 描述和要求保护其他实施例。

公开(公告)号：US07390947B2

公开(公告)日：2008-06-24

申请号：US11037512

申请日：2005-01-18

Applicant: Amlan Majumdar ,  Justin K. Brask ,  Marko Radosavljevic ,  Suman Datta ,  Brian S. Doyle ,  Mark L. Doczy ,  Jack Kavalieros ,  Matthew V. Metz ,  Robert S. Chau ,  Uday Shah ,  James Blackwell

Inventor： Amlan Majumdar ,  Justin K. Brask ,  Marko Radosavljevic ,  Suman Datta ,  Brian S. Doyle ,  Mark L. Doczy ,  Jack Kavalieros ,  Matthew V. Metz ,  Robert S. Chau ,  Uday Shah ,  James Blackwell

IPC: H01L29/12

CPC classification number: B82Y10/00 ,  H01L29/0665 ,  H01L29/0673 ,  H01L29/1606 ,  H01L51/0048 ,  H01L51/0052 ,  H01L51/0541 ,  H01L51/0545 ,  Y10S977/701 ,  Y10S977/938

Abstract: A nanotube transistor, such as a carbon nanotube transistor, may be formed with a top gate electrode and a spaced source and drain. Conduction along the transistor from source to drain is controlled by the gate electrode. Underlying the gate electrode are at least two nanotubes. In some embodiments, the substrate may act as a back gate.

Abstract translation: 诸如碳纳米管晶体管的纳米管晶体管可以形成有顶栅电极和间隔开的源极和漏极。 沿晶体管从源极到漏极的导通由栅电极控制。 栅电极底部至少有两个纳米管。 在一些实施例中，衬底可用作背栅。

公开(公告)号：US20070090408A1

公开(公告)日：2007-04-26

申请号：US11240487

申请日：2005-09-29

Applicant: Amlan Majumdar ,  Suman Datta ,  Brian Doyle ,  Jack Kavalieros ,  Justin Brask ,  Matthew Metz ,  Marko Radosavljevic ,  Been-Yih Jin ,  Robert Chau

Inventor： Amlan Majumdar ,  Suman Datta ,  Brian Doyle ,  Jack Kavalieros ,  Justin Brask ,  Matthew Metz ,  Marko Radosavljevic ,  Been-Yih Jin ,  Robert Chau

IPC: H01L29/76

CPC classification number: H01L29/66795 ,  H01L29/66545 ,  H01L29/785 ,  H01L29/7854

Abstract: A field-effect transistor for a narrow-body, multiple-gate transistor such as a FinFET, tri-gate or Ω-FET is described. The corners of the channel region disposed beneath the gate are rounded n, for instance, oxidation steps, to reduce the comer effect associated with conduction initiating in the corners of the channel region.

Abstract translation: 描述了用于诸如FinFET，三栅极或者Omega-FET的窄体多栅极晶体管的场效应晶体管。 设置在栅极下方的通道区域的角部是圆形的，例如氧化步骤，以减少与沟道区域的拐角中的传导起始相关的拐角效应。

公开(公告)号：US20060286755A1

公开(公告)日：2006-12-21

申请号：US11154138

申请日：2005-06-15

Applicant: Justin Brask ,  Robert Chau ,  Suman Datta ,  Mark Doczy ,  Brian Doyle ,  Jack Kavalieros ,  Amlan Majumdar ,  Matthew Metz ,  Marko Radosavljevic

Inventor： Justin Brask ,  Robert Chau ,  Suman Datta ,  Mark Doczy ,  Brian Doyle ,  Jack Kavalieros ,  Amlan Majumdar ,  Matthew Metz ,  Marko Radosavljevic

IPC: H01L31/119 ,  H01L31/113 ,  H01L31/062 ,  H01L29/94 ,  H01L29/76 ,  H01L21/336

CPC classification number: H01L29/7848 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/1033 ,  H01L29/161 ,  H01L29/165 ,  H01L29/24 ,  H01L29/267 ,  H01L29/4236 ,  H01L29/42376 ,  H01L29/4966 ,  H01L29/66545 ,  H01L29/66621 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/66818 ,  H01L29/7834 ,  H01L29/7838 ,  H01L29/785 ,  H04B1/3827 ,  Y10S438/926

Abstract: A method of fabricating a MOS transistor having a thinned channel region is described. The channel region is etched following removal of a dummy gate. The source and drain regions have relatively low resistance with the process.

Abstract translation: 描述了制造具有减薄沟道区的MOS晶体管的方法。 在去除虚拟栅极之后蚀刻沟道区。 源极和漏极区域具有相对较低的电阻。