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公开(公告)号：US10078182B2
公开(公告)日：2018-09-18
申请号：US15243746
申请日：2016-08-22
Inventor： Shinichi Watanuki , Akira Mitsuiki , Atsuro Inada , Tohru Mogami , Tsuyoshi Horikawa , Keizo Kinoshita
CPC classification number: G02B6/136 , G02B6/12004 , G02B6/122 , G02B2006/12061 , G02B2006/12097 , G02F1/025 , G02F2201/063 , G02F2201/066 , G02F2202/105
Abstract: When an optical waveguide is formed, an area of an opening of a resist mask is equal to an area of a semiconductor layer for a dummy pattern exposed from the resist mask, and the semiconductor layer for the dummy pattern exposed from the resist mask has a uniform thickness in a region in which the dummy pattern is formed. As a result, an effective pattern density does not change in etching the semiconductor layer for the dummy pattern, and accordingly, it is possible to form a rib-shaped optical waveguide having desired dimensions and a desired shape.
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公开(公告)号：US20180067260A1
公开(公告)日：2018-03-08
申请号：US15692062
申请日：2017-08-31
Inventor： Tsuyoshi HORIKAWA , Tohru MOGAMI , Keizo KINOSHITA
CPC classification number: G02B6/132 , C23C14/083 , C23C14/48 , G02B6/122 , G02B2006/12061
Abstract: Provided is an optical waveguide circuit avoiding the difficulty of the property compensation based on temperature control, compensated with respect to the property variations due to fabrication error, particularly paid attention in a silicon waveguide, and being low in power consumption and high in performances. The optical waveguide circuit includes a silicon (Si) substrate, a buried oxide film (BOX) layer formed on the Si substrate, and an SOI (Silicon on Insulator) layer, formed on the BOX layer, including an optical element utilizing the SOI layer as a main optical transmission medium. At least part of a waveguide of the optical element includes uniformly distributed and thermally unstable crystal defects.
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公开(公告)号：US09874768B2
公开(公告)日：2018-01-23
申请号：US15463177
申请日：2017-03-20
Inventor： Takeshi Baba , Tatsuya Usuki , Suguru Akiyama
CPC classification number: G02F1/0121 , G02F1/025 , G02F1/2257 , G02F2001/0152 , G02F2001/212
Abstract: An optical modulation device includes: an optical waveguide formed above a substrate; a phase modulator disposed on part of the optical waveguide; a capacitor connected to the phase modulator and including a lower electrode and an upper electrode; a resistor connected in parallel to the capacitor; and an appended part integrated with the upper electrode and electrically connected to the resistor, wherein the appended part is smaller in area than the capacitor (upper electrode).
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74.发明授权公开(公告)号：US09874709B2
公开(公告)日：2018-01-23
申请号：US14955600
申请日：2015-12-01
Inventor： Akinori Hayakawa
CPC classification number: G02B6/4295 , G02B6/2726 , G02B6/2934 , G02B6/29382 , G02B2006/12138 , G02B2006/12142
Abstract: An optical functional device includes: a photodetector; a first optical waveguide which is connected to one end face of the photodetector; and a second optical waveguide which is connected to the other end face of the photodetector. The photodetector is formed in a multi-mode interferometer and has electrodes. Light input from the first optical waveguide to the photodetector focuses image at a position physically away from the second optical waveguide, and light input from the second optical waveguide to the photodetector focuses image at a position physically away from the first optical waveguide.
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75.发明申请公开(公告)号：US20180010906A1
公开(公告)日：2018-01-11
申请号：US15641384
申请日：2017-07-05
Inventor： Masatoshi TOKUSHIMA
IPC: G01B11/14
CPC classification number: G01B11/14 , G01B11/272 , G02B6/00 , G02B6/305 , G02B6/34 , G02B6/422 , G02B6/4222 , G02B6/4225 , G03F9/70
Abstract: An alignment optical measurement element includes a grating coupler, and a reflector coupled to the grating coupler. The alignment optical measurement element is arranged so that: the grating coupler diffracts an incident light in a first direction into a first diffracted light to propagate the first diffracted light as a first propagating light in a second direction, the reflector reflects the first propagating light into a second propagating light in a third direction opposite to the second direction; and the grating coupler diffracts the second propagating light into a second diffracted light to emit the second diffracted light as an emitted light in a fourth direction opposite to the first direction.
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Patent Agency Ranking
公开(公告)号：US09775245B2
公开(公告)日：2017-09-26
申请号：US15128904
申请日：2015-03-18
Inventor： Takeshi Akagawa , Kenichiro Yashiki
CPC classification number: H05K1/111 , G02B6/122 , G02B6/4232 , H01L23/49844 , H01L2224/16225 , H05K1/0219 , H05K1/0243 , H05K1/0245 , H05K1/0251 , H05K1/181 , H05K3/4688 , H05K2201/10121 , H05K2201/10734 , Y02P70/611
Abstract: A pad-array arrangement structure on a substrate for mounting an IC chip on the substrate, wherein a structure with which it is possible to maximally avoid an increase in the number of wiring layers on the substrate is obtained by devising the pad arrangement in an IC pad-array region.A embodiment of the present invention provides a pad-array structure on a substrate for mounting an IC chip on the substrate. The present invention is characterized in that: a plurality of ground pads arrayed equidistantly in a first row, and a plurality of signal pads arrayed equidistantly in a second row on the inside of and parallel to the first row, are provided on a first circumferential edge in the pad-array region; each of the signal pads passes between two adjacent ground pads in the first row and is connected to an external circuit on the substrate; and electrical signals are input to and output from the external circuit.
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公开(公告)号：US20170105284A1
公开(公告)日：2017-04-13
申请号：US15128904
申请日：2015-03-18
Inventor： Takeshi AKAGAWA , Kenichiro YASHIKI
CPC classification number: H05K1/111 , G02B6/122 , G02B6/4232 , H01L23/49844 , H01L2224/16225 , H05K1/0219 , H05K1/0243 , H05K1/0245 , H05K1/0251 , H05K1/181 , H05K3/4688 , H05K2201/10121 , H05K2201/10734 , Y02P70/611
Abstract: A pad-array arrangement structure on a substrate for mounting an IC chip on the substrate, wherein a structure with which it is possible to maximally avoid an increase in the number of wiring layers on the substrate is obtained by devising the pad arrangement in an IC pad-array region.A embodiment of the present invention provides a pad-array structure on a substrate for mounting an IC chip on the substrate. The present invention is characterized in that: a plurality of ground pads arrayed equidistantly in a first row, and a plurality of signal pads arrayed equidistantly in a second row on the inside of and parallel to the first row, are provided on a first circumferential edge in the pad-array region; each of the signal pads passes between two adjacent ground pads in the first row and is connected to an external circuit on the substrate; and electrical signals are input to and output from the external circuit.
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公开(公告)号：US09615152B2
公开(公告)日：2017-04-04
申请号：US14730680
申请日：2015-06-04
Inventor： Seokhwan Jeong
CPC classification number: H04Q11/0005 , H04B10/0795 , H04B10/60 , H04B10/67 , H04B10/676 , H04J14/02 , H04J14/06 , H04Q2011/0015 , H04Q2011/0016 , H04Q2011/0035
Abstract: An optical element includes: a polarization splitter that splits light input from an input port into a first signal and a second signal according to a plane of polarization; a polarization rotator that rotates a plane of polarization of the second signal output from the polarization splitter by 90 degrees; a first optical coupler that combines the first signal output from the polarization splitter and the second signal output from the polarization rotator and splits the resultant signal into a third signal and a fourth signal with an equal amplitude; a phase controller that controls a phase of the third signal; and a second optical coupler that combines the third signal output from the phase controller and the fourth signal output from the first optical coupler and splits the resultant signal into a fifth signal and a sixth signal with an equal amplitude.
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公开(公告)号：US20170068051A1
公开(公告)日：2017-03-09
申请号：US15243746
申请日：2016-08-22
Inventor： Shinichi WATANUKI , Akira MITSUIKl , Atsuro INADA , Tohru MOGAMI , Tsuyoshi HORIKAWA , Keizo KINOSHITA
CPC classification number: G02B6/136 , G02B6/12004 , G02B6/122 , G02B2006/12061 , G02B2006/12097 , G02F1/025 , G02F2201/063 , G02F2201/066 , G02F2202/105
Abstract: When an optical waveguide is formed, an area of an opening of a resist mask is equal to an area of a semiconductor layer for a dummy pattern exposed from the resist mask, and the semiconductor layer for the dummy pattern exposed from the resist mask has a uniform thickness in a region in which the dummy pattern is formed. As a result, an effective pattern density does not change in etching the semiconductor layer for the dummy pattern, and accordingly, it is possible to form a rib-shaped optical waveguide having desired dimensions and a desired shape.
Abstract translation: 当形成光波导时，抗蚀剂掩模的开口面积等于从抗蚀剂掩模露出的虚拟图案的半导体层的面积，并且从抗蚀剂掩模露出的伪图案的半导体层具有 在其中形成虚拟图案的区域中具有均匀的厚度。 结果，对于伪图案的半导体层的蚀刻，有效图案密度不变，因此，可以形成具有所需尺寸和期望形状的肋状光波导。
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公开(公告)号：US20160170157A1
公开(公告)日：2016-06-16
申请号：US14904038
申请日：2014-07-09
Inventor： Shigeki TAKAHASHI
CPC classification number: G02B6/4209 , G02B6/122 , G02B6/1228 , G02B6/2804 , G02B6/29344 , G02B2006/12121
Abstract: A low-cost optical circuit, in which influence of reflected light is reduced, is provided. According to an embodiment of the present invention, an optical circuit (200) comprises a first optical coupler (204A) having at least two outputs, and a second optical coupler (204B) coupled to at least one of the outputs of the first optical coupler (204A), and wherein the ratio of an intensity of light reflected from the first optical coupler (204A) to an intensity of light inputted to the first optical coupler is smaller than the ratio of an intensity of light reflected from the second optical coupler (204B) to an intensity of light inputted to the second optical coupler.
Abstract translation: 提供了其中减少了反射光的影响的低成本光学电路。 根据本发明的实施例，光电路（200）包括具有至少两个输出的第一光耦合器（204A）和耦合到第一光耦合器的至少一个输出端的第二光耦合器（204B） （204A），并且其中从所述第一光耦合器（204A）反射的光的强度与输入到所述第一光耦合器的光的强度之比小于从所述第二光耦合器（204A）反射的光的强度的比 204B）输入到第二光耦合器的光强度。
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