公开(公告)号：US06449211B1

公开(公告)日：2002-09-10

申请号：US09945021

申请日：2001-08-31

Applicant: Owen W. Jungroth ,  Rajesh Sundaram ,  Mase J. Taub ,  Rupinder K. Bains ,  Raymond Zeng ,  Binh N. Ngo ,  Bharat Pathak

Inventor： Owen W. Jungroth ,  Rajesh Sundaram ,  Mase J. Taub ,  Rupinder K. Bains ,  Raymond Zeng ,  Binh N. Ngo ,  Bharat Pathak

IPC: G11C800

CPC classification number: G11C16/30 ,  G11C5/147 ,  G11C8/08

Abstract: A circuit includes (i) an N-channel device having a gate, a source connected to low voltage, and a drain connected to a memory select gate, (ii) a P-channel device having a gate, a source, and a drain connected to the drain of the N-channel device, and (iii) a voltage supply connected to the source of the P-channel device, the voltage supply switching between a first high voltage and a first lower voltage. A gate driver supplies, to the gates of the N-channel and P-channel devices, a second high voltage, a second low voltage, or an intermediary voltage between the second high voltage and second low voltage. The gate driver supplies the intermediary voltage when the voltage supply switches between the first high voltage and first lower voltage.

Abstract translation: 电路包括（i）具有栅极，连接到低电压的源极和连接到存储器选择栅极的漏极的N沟道器件，（ii）具有栅极，源极和漏极的P沟道器件 连接到N沟道器件的漏极，以及（iii）连接到P沟道器件源极的电压源，电压源在第一高电压和第一较低电压之间切换。 栅极驱动器向N沟道和P沟道器件的栅极提供第二高电压，第二低电压或第二高电压和第二低电压之间的中间电压。 当电源在第一高电压和第一低电压之间切换时，栅极驱动器提供中间电压。

公开(公告)号：US06434073B1

公开(公告)日：2002-08-13

申请号：US09924888

申请日：2001-08-07

Applicant: Sandeep K. Guliani ,  Rajesh Sundaram ,  Mase J. Taub

Inventor： Sandeep K. Guliani ,  Rajesh Sundaram ,  Mase J. Taub

IPC: G11C702

Abstract: A method for a VPX banked architecture. The method of one embodiment first segments a memory array into at least two banks. Each bank including memory cells. The banks are provided with a supply voltage.

公开(公告)号：US06359814B1

公开(公告)日：2002-03-19

申请号：US09753351

申请日：2000-12-29

Applicant: Rajesh Sundaram ,  Kerry D. Tedrow

Inventor： Rajesh Sundaram ,  Kerry D. Tedrow

IPC: G11C700

CPC classification number: H02M3/07 ,  G11C11/22 ,  H02M2003/071

Abstract: A negative voltage charge pump including a regulation circuit. The regulation circuit has a level shift ladder including a plurality of level shifters connected in series. One end of the level shift ladder receives a power supply voltage and the other end receives the negative output of the charge pump. A feedback voltage is generated from one of the intermediate nodes of the level shift ladder. A differential amplifier generates a regulation voltage which varies as a function of the feedback voltage and a reference voltage. The regulation voltage is applied to a frequency control input of a voltage-controlled oscillator for generating a signal that drives the charge pump. Each of the level shifters of the level shift ladder can be a triple well device that can be configured to handle negative voltages without forward biasing an internal p-n junction.

Abstract translation: 负电压电荷泵，包括调节电路。 调节电路具有包括串联连接的多个电平移位器的电平移位梯形图。 电平转换梯的一端接收电源电压，另一端接收电荷泵的负输出。 从电平转换梯的中间节点之一产生反馈电压。 差分放大器产生作为反馈电压和参考电压的函数而变化的调节电压。 调节电压被施加到压控振荡器的频率控制输入端，用于产生驱动电荷泵的信号。 电平变换梯级的每个电平移位器可以是三阱器件，其可被配置为处理负电压而不向前偏置内部p-n结。

公开(公告)号：US20170060202A1

公开(公告)日：2017-03-02

申请号：US14837372

申请日：2015-08-27

Applicant: RAJESH SUNDARAM ,  MUTHUKUMAR P. SWAMINATHAN ,  DOYLE RIVERS

Inventor： RAJESH SUNDARAM ,  MUTHUKUMAR P. SWAMINATHAN ,  DOYLE RIVERS

IPC: G06F1/20 ,  G05D23/19

CPC classification number: G06F1/206 ,  G06F1/3225 ,  G06F1/3275

Abstract: Data reliability and integrity may be compromised when memory resources used to store the data reach elevated temperatures. A sensor in the memory resource may monitor the temperature of the memory resource in real-time. A comparator in the memory resource may indicate a high temperature condition to a memory controller. The memory controller, in response to the high temperature condition, can restrict or halt data flow to the memory resource. When the real-time temperature of the memory resource falls below a defined threshold, the memory controller may resume data flow to the memory resource.

Abstract translation: 当用于存储数据的内存资源达到升高的温度时，数据的可靠性和完整性可能会受到影响。 存储器资源中的传感器可以实时监视存储器资源的温度。 存储器资源中的比较器可以指示存储器控制器的高温状态。 存储器控制器响应于高温条件，可以限制或停止到存储器资源的数据流。 当存储器资源的实时温度低于定义的阈值时，存储器控制器可以恢复到存储器资源的数据流。

公开(公告)号：US20140317474A1

公开(公告)日：2014-10-23

申请号：US13997246

申请日：2011-12-30

Applicant: Shekoufeh Qawami ,  Rajesh Sundaram

Inventor： Shekoufeh Qawami ,  Rajesh Sundaram

IPC: G06F11/10

CPC classification number: G06F11/1048 ,  G06F11/073 ,  G06F11/0763 ,  G06F11/1068 ,  G11C13/0004

Abstract: Methods and apparatus related to PCMS (Phase Change Memory with Switch) write error detection are described. In one embodiment, a first storage unit stores a single bit to indicate whether an error corresponding to a write operation in any of one or more PCMS devices has occurred. Also, one or more storage units each store a plurality of bits to indicate whether the error corresponding to the write operation has occurred in a partition of a plurality of partitions of the one or more PCMS devices. Other embodiments are also disclosed and claimed.

Abstract translation: 描述了与PCMS（带切换的相变存储器）写入错误检测相关的方法和装置。 在一个实施例中，第一存储单元存储单个位以指示是否发生了与一个或多个PCMS设备中的任一个中的写入操作相对应的错误。 此外，一个或多个存储单元每个存储多个位以指示与一个或多个PCMS设备的多个分区的分区中是否发生了与写入操作相对应的错误。 还公开并要求保护其他实施例。

公开(公告)号：US20120120722A1

公开(公告)日：2012-05-17

申请号：US12946612

申请日：2010-11-15

Applicant: Rajesh Sundaram ,  Derchang Kau ,  David J. Zimmerman

Inventor： Rajesh Sundaram ,  Derchang Kau ,  David J. Zimmerman

IPC: G11C11/21

CPC classification number: G11C13/0004 ,  G06F2213/0038 ,  G11C7/1039 ,  G11C13/0061 ,  G11C13/0069

Abstract: An apparatus for data storage is presented. In one embodiment, the apparatus includes a phase change memory device comprising phase change memory storage elements. The apparatus further includes control logic to control two or more set pipelines to serve memory requests in a staggered manner, such that set operations of the memory requests begin at different times.

Abstract translation: 提出了一种用于数据存储的设备。 在一个实施例中，该装置包括包括相变存储器存储元件的相变存储器件。 该装置还包括控制逻辑以控制两个或更多个集合管线以交错方式提供存储器请求，使得存储器请求的设置操作在不同时间开始。

公开(公告)号：US20110196905A1

公开(公告)日：2011-08-11

申请号：US13087710

申请日：2011-04-15

Applicant: Jeffrey S. Kimmel ,  Rajesh Sundaram ,  George Totolos, JR. ,  Michael W.J. Hordijk

Inventor： Jeffrey S. Kimmel ,  Rajesh Sundaram ,  George Totolos, JR. ,  Michael W.J. Hordijk

IPC: G06F17/30

CPC classification number: G06F12/0246 ,  G06F11/1666 ,  G06F11/20 ,  G06F2212/1032 ,  G06F2212/7208 ,  G11C29/76

Abstract: Described herein are method and apparatus for storing data to a low-latency random read memory (LLRRM) device using non-aligned data striping, the LLRRM device being implemented on a storage system. The LLRRM device may comprise a bank comprising a plurality of memory chips, each chip being simultaneously accessible for storing data on a plurality of erase-units (EUs). A storage operating system may maintain, for each chip, a reserve data structure listing reserve EUs and a remapping data structure for tracking remappings between defective EUs to reserve EUs in the chip. A defective EU in a chip may be mapped to a reserve EU from the reserve data structure. Upon receiving a data block to be stored to the LLRRM device at the defective EU, the storage operating system may stripe the received data block across a plurality of chips in a non-aligned manner using the remapped reserve EU.

Abstract translation: 这里描述了使用非对齐数据条带化将数据存储到低延迟随机读取存储器（LLRRM）装置的方法和装置，LLRRM装置在存储系统上实现。 LLRRM设备可以包括一个包括多个存储器芯片的存储体，每个芯片可以同时访问以存储多个擦除单元（EU）上的数据。 存储操作系统可以为每个芯片保留列出保留EU的备用数据结构和用于跟踪缺陷EU之间的重新映射的重映射数据结构，以在芯片中保留EU。 芯片中的有缺陷的EU可以从保留数据结构映射到保留EU。 在接收到在缺陷EU处存储到LLRRM设备的数据块时，存储操作系统可以使用重新映射的保留EU以不对齐的方式跨越多个芯片对接收到的数据块进行条带化。

公开(公告)号：US07693157B2

公开(公告)日：2010-04-06

申请号：US11410349

申请日：2006-04-25

Applicant: Khawar M. Zuberi ,  Mathias Jourdain ,  Rajesh Sundaram

Inventor： Khawar M. Zuberi ,  Mathias Jourdain ,  Rajesh Sundaram

IPC: H04L12/28

CPC classification number: H04L47/2416 ,  H04L43/50 ,  H04L45/125 ,  H04L45/302 ,  H04L45/70 ,  H04L47/15 ,  H04L47/70 ,  H04L47/762 ,  H04L47/803 ,  H04L47/822 ,  H04L47/824

Abstract: An access control mechanism in a network connecting one or more sink devices to a server providing audio/visual data (A/V) in streams. As a sink device requests access, the server measures available bandwidth to the sink device. If the measurement of available bandwidth is completed before the sink device requests a stream of audio/visual data, the measured available bandwidth is used to set transmission parameters of the data stream in accordance with a Quality of Service (QoS) policy. If the measurement is not completed when the data stream is requested, the data stream is nonetheless transmitted. In this scenario, the data stream may be transmitted using parameters computed using a cached measurement of the available bandwidth to the sink device. If no cached measurement is available, the data stream is transmitted with a low priority until a measurement can be made. Once the measurement is available, the transmission parameters of the data stream are re-set. With this access control mechanism, A/V streams may be provided with low latency but with transmission parameters accurately set in accordance with the QoS policy.

Abstract translation: 将一个或多个宿设备连接到提供流中的音频/视频数据（A / V）的服务器的网络中的访问控制机制。 作为宿设备请求访问，服务器测量宿设备的可用带宽。 如果在信宿设备请求音频/视频数据流之前完成可用带宽的测量，则测量的可用带宽被用于根据服务质量（QoS）策略来设置数据流的传输参数。 如果在请求数据流时测量未完成，则数据流仍然被传输。 在这种情况下，可以使用使用可用带宽的缓存测量计算的参数向宿设备发送数据流。 如果没有缓存测量可用，则数据流以低优先级发送，直到可以进行测量。 一旦测量可用，数据流的传输参数被重新设置。 利用这种访问控制机制，可以提供低延迟的A / V流，但是根据QoS策略准确地设置传输参数。

公开(公告)号：US07609562B2

公开(公告)日：2009-10-27

申请号：US11701302

申请日：2007-01-31

Applicant: Rajesh Sundaram

Inventor： Rajesh Sundaram

IPC: G11C16/04 ,  G11C7/22 ,  G11C7/10 ,  G06F12/06

CPC classification number: G11C5/04 ,  G11C16/08

Abstract: Various embodiments of the invention may use one or more programmable non-volatile registers in each memory device to provide a separate device address for that device. These registers may be programmed at various points in the manufacturing and distribution cycle, such as but not limited to the memory chip factory, an original equipment manufacturer (OEM), or in the field. In some embodiments, other types of information (e.g., configuration information for the memory device) may also be programmed in this manner.

Abstract translation: 本发明的各种实施例可以使用每个存储器设备中的一个或多个可编程非易失性寄存器来为该设备提供单独的设备地址。 这些寄存器可以在制造和分发周期的各个点进行编程，例如但不限于存储器芯片工厂，原始设备制造商（OEM）或现场。 在一些实施例中，也可以以这种方式编程其他类型的信息（例如，存储器件的配置信息）。

公开(公告)号：US07587630B1

公开(公告)日：2009-09-08

申请号：US11118674

申请日：2005-04-29

Applicant: Loellyn Cassell ,  Atul Goel ,  James Leong ,  Rajesh Sundaram

Inventor： Loellyn Cassell ,  Atul Goel ,  James Leong ,  Rajesh Sundaram

IPC: G06F11/00

CPC classification number: G06F11/1088

Abstract: A method and system for rapidly recovering data from a failed disk in a RAID disk group are disclosed. According to one aspect of the present invention, a RAID-based storage system identifies a particular disk in a RAID disk group as a “dead” disk (e.g., incapable of servicing client-initiated requests in a timely manner). Accordingly, a spare disk is allocated to replace the “dead” disk and client-initiated read/write requests are directed to the spare disk for servicing. In addition, a disk-to-disk copy operation is initiated. Without overwriting valid data on the target disk with stale data from the “dead” disk, the disk-to-disk copy operation copies data from the “dead” disk to the target by directly reading data from the “dead” disk while reconstructing only the data that cannot be read directly from the “dead” disk.

Abstract translation: 公开了一种用于从RAID磁盘组中的故障磁盘快速恢复数据的方法和系统。 根据本发明的一个方面，基于RAID的存储系统将RAID磁盘组中的特定磁盘识别为“死”磁盘（例如，不能及时地为客户端发起的请求提供服务）。 因此，分配备用磁盘来替换“死”磁盘，并且客户端发起的读/写请求被引导到备用磁盘进行维修。 此外，启动磁盘到磁盘复制操作。 没有使用来自“死”磁盘的陈旧数据覆盖目标磁盘上的有效数据，磁盘到磁盘复制操作通过直接从“死”磁盘读取数据而将数据从“死”磁盘复制到目标磁盘，而仅重新构建 无法从“死”磁盘读取的数据。