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    FLEXIBLE IDENTIFICATION TECHNIQUE
    1.
    发明申请
    FLEXIBLE IDENTIFICATION TECHNIQUE 有权
    灵活识别技术

    公开(公告)号：US20140362657A1

    公开(公告)日：2014-12-11

    申请号：US13910632

    申请日：2013-06-05

    申请人： Julie M. Walker ,  Doyle Rivers

    发明人： Julie M. Walker ,  Doyle Rivers

    IPC分类号： G11C8/04

    CPC分类号： G11C8/04 ,  G11C5/14 ,  G11C8/06 ,  G11C8/12 ,  G11C16/20

    摘要： A shared-signaling multi-device memory system is capable of changing between addressing modes without the multi-device memory being required to undergo a power cycle. First and second registers of a memory device are set to both contain first address-identification information in response a first address-assignment command that is received a power cycle. The first register is set to contain second address-identification information in response a second address-assignment command that is received subsequently to the first address assignment command. Depending on the value of the second address-identification information, the memory device is configured in an individual-device-addressing mode or a parallel addressing mode without a power cycle. The first register can be reset to the first address-identification information contained in the second register in response to an address-restore command without a power cycle. A corresponding method is also disclosed.

    摘要翻译： 共享信令多设备存储器系统能够在寻址模式之间改变，而不需要多器件存储器来进行功率循环。 存储器件的第一和第二寄存器被设置为响应于接收到功率周期的第一地址分配命令而包含第一地址识别信息。 响应于在第一地址分配命令之后接收到的第二地址分配命令，将第一寄存器设置为包含第二地址识别信息。 取决于第二地址识别信息的值，存储器件被配置为单个设备寻址模式或并行寻址模式而没有功率循环。 响应于没有电源循环的地址恢复命令，第一寄存器可以被重置为包含在第二寄存器中的第一地址识别信息。 还公开了相应的方法。

    DRAIN SELECT GATE VOLTAGE MANAGEMENT
    3.
    发明申请
    DRAIN SELECT GATE VOLTAGE MANAGEMENT 有权
    排水门电压管理

    公开(公告)号：US20110216600A1

    公开(公告)日：2011-09-08

    申请号：US12715530

    申请日：2010-03-02

    申请人： Akira Goda ,  Pranav Kalavade ,  Doyle Rivers

    发明人： Akira Goda ,  Pranav Kalavade ,  Doyle Rivers

    IPC分类号： G11C16/04

    CPC分类号： G11C16/12 ,  G11C16/04 ,  G11C16/0433

    摘要： Some embodiments include apparatus, systems, and methods that operate to apply a first value of a drain select gate voltage during a first portion of a programming time period associated with programming a plurality of memory cells, and to apply a second value of the drain select gate voltage different from the first value during a second, subsequent portion of the programming time period. The drain select gate voltage may be changed between groups of programming pulses in a single programming cycle. The first and second portions may be determined according to the number of applied programming pulses, the number of memory cells that have been completely programmed, and/or other conditions. Additional apparatus, systems, and methods are disclosed.

    摘要翻译： 一些实施例包括在与编程多个存储器单元相关联的编程时间周期的第一部分期间操作以施加漏极选择栅极电压的第一值的装置，系统和方法，以及施加漏极选择的第二值 在第二编程时间段的后续部分中，栅极电压与第一值不同。 漏极选择栅极电压可以在单个编程周期中的编程脉冲组之间改变。 第一和第二部分可以根据应用的编程脉冲的数量，已经完全编程的存储器单元的数量和/或其他条件来确定。 公开了附加装置，系统和方法。

    Isolating, at least in part, local row or column circuitry of memory cell before establishing voltage differential to permit reading of cell
    5.
    发明授权
    Isolating, at least in part, local row or column circuitry of memory cell before establishing voltage differential to permit reading of cell 有权
    至少部分地在建立电压差之前隔离存储单元的本地行或列电路，以允许读取单元

    公开(公告)号：US09030906B2

    公开(公告)日：2015-05-12

    申请号：US13995230

    申请日：2012-06-06

    申请人： Doyle Rivers ,  Prashant S. Damle ,  Raymond W. Zeng

    发明人： Doyle Rivers ,  Prashant S. Damle ,  Raymond W. Zeng

    IPC分类号： G11C8/00 ,  G11C13/00 ,  G11C7/02

    CPC分类号： G11C13/0004 ,  G11C7/02 ,  G11C13/004

    摘要： An embodiment may include local row and column circuitry that are local to a memory cell of a memory device. Either the local row circuitry or the local column circuitry may be electrically isolated, at least in part, from at least one remaining portion of the memory device during the establishing of a voltage differential between the local row circuitry and the local column circuitry that is to permit the memory cell to be read during a read of the memory cell. The read may occur subsequent to the establishing of the voltage differential. Many variations, modifications, and alternatives are possible without departing from this embodiment.

    摘要翻译： 实施例可以包括对存储器件的存储器单元本地的本地行和列电路。 在本地行电路和本地列电路之间的电压差建立期间，本地行电路或本地列电路可以至少部分地与存储器件的至少一个剩余部分电隔离， 允许在存储器单元的读取期间读取存储器单元。 读取可能在建立电压差之后发生。 在不脱离本实施例的情况下，可以进行许多变化，修改和替换。

    Reducing effects of erase disturb in a memory device
    8.
    发明授权
    Reducing effects of erase disturb in a memory device 有权
    减少存储器件中擦除干扰的影响

    公开(公告)号：US08203876B2

    公开(公告)日：2012-06-19

    申请号：US12628522

    申请日：2009-12-01

    申请人： Akira Goda ,  Alessandro Torsi ,  Carlo Musilli ,  Mark A. Helm ,  Doyle Rivers

    发明人： Akira Goda ,  Alessandro Torsi ,  Carlo Musilli ,  Mark A. Helm ,  Doyle Rivers

    IPC分类号： G11C16/04

    CPC分类号： G11C16/3418 ,  G11C16/0483 ,  G11C16/14

    摘要： Methods for programming and memory devices are disclosed. One such method for programming includes initially biasing a subset of a plurality of control gates of a string of memory cells with a negative voltage, wherein the subset is less than all of the plurality of control gates of the string. The control gate of a selected memory cell is subsequently biased with a programming voltage during a programming phase.

    摘要翻译： 公开了用于编程和存储器件的方法。 一种用于编程的方法包括：初始地利用负电压偏置存储器单元串的多个控制栅极的子集，其中该子集小于该串的多个控制栅极的全部。 在编程阶段期间，所选择的存储单元的控制栅随后用编程电压进行偏置。