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    Substantially enzyme free personal wash compositions comprising non-silicates with basal layer cationic charge
    72.
    发明申请
    Substantially enzyme free personal wash compositions comprising non-silicates with basal layer cationic charge 失效
    基本上无酶的个人洗涤组合物，其包含具有基础层阳离子电荷的非硅酸盐

    公开(公告)号：US20060025319A1

    公开(公告)日：2006-02-02

    申请号：US10902202

    申请日：2004-07-29

    申请人： Vivek Subramanian ,  Pravin Shah ,  Kavssery Ananthapadmanabhan

    发明人： Vivek Subramanian ,  Pravin Shah ,  Kavssery Ananthapadmanabhan

    IPC分类号： A61K8/00

    CPC分类号： A61K8/26 ,  A61Q19/10

    摘要： The present invention relates to personal wash compositions comprising, non-silicate particles, wherein the basal layer(s) carries a net cationic charge. The use of these specific particles results in enhanced properties (e.g., enhanced foaming, hydrotroping) of the personal wash products. The invention further discloses process for decreasing viscosity and/or increasing foam comprising formulating compositions with non-silicate layer compounds as specified.

    摘要翻译： 本发明涉及包含非硅酸盐颗粒的个人洗涤组合物，其中基底层承载净阳离子电荷。 这些特定颗粒的使用导致个人洗涤产品的增强的性能（例如，增强的起泡，水解加工）。 本发明进一步公开了降低粘度和/或增加泡沫的方法，其中包括按照规定的非硅酸盐层化合物配制组合物。

    Low cost three-dimensional memory array
    73.
    发明授权
    Low cost three-dimensional memory array 有权
    低成本三维存储阵列

    公开(公告)号：US06515888B2

    公开(公告)日：2003-02-04

    申请号：US09928969

    申请日：2001-08-13

    申请人： Mark G. Johnson ,  Thomas H. Lee ,  Vivek Subramanian ,  P. Michael Farmwald ,  N. Johan Knall

    发明人： Mark G. Johnson ,  Thomas H. Lee ,  Vivek Subramanian ,  P. Michael Farmwald ,  N. Johan Knall

    IPC分类号： G11C1100

    CPC分类号： H01L27/101 ,  G11C17/16 ,  H01L27/0688

    摘要： A low-cost memory cell array includes multiple, vertically-stacked layers of memory cells. In one form, each memory cell is characterized by a small cross-sectional area and a read current less than 6.3 microamperes. The resulting memory array has a slow access time and is well-suited for digital media storage, where access time requirements are low and the dramatic cost reductions associated with the disclosed memory arrays are particularly attractive. In another form, each memory cell includes an antifuse layer and diode components, wherein at least one diode component is heavily doped (to a dopant concentration greater than 1019/cm3), and wherein the read current is large (up to 500 mA).

    摘要翻译： 低成本存储单元阵列包括多个垂直堆叠的存储单元层。 在一种形式中，每个存储单元的特征在于小的横截面积和小于6.3微安培的读取电流。 所得到的存储器阵列具有缓慢的访问时间，并且非常适合于数字媒体存储，其中访问时间要求低，并且与所公开的存储器阵列相关联的显着的成本降低特别有吸引力。 在另一种形式中，每个存储器单元包括反熔丝层和二极管部件，其中至少一个二极管部件被重掺杂（掺杂浓度大于1019 / cm3），并且其中读取电流大（高达500mA）。

    Integrated circuit structure including three-dimensional memory array
    75.
    发明授权
    Integrated circuit structure including three-dimensional memory array 有权
    集成电路结构包括三维存储阵列

    公开(公告)号：US06385074B1

    公开(公告)日：2002-05-07

    申请号：US09748816

    申请日：2000-12-22

    申请人： Mark G. Johnson ,  Thomas H. Lee ,  Vivek Subramanian ,  Paul Michael Farmwald ,  James M. Cleeves

    发明人： Mark G. Johnson ,  Thomas H. Lee ,  Vivek Subramanian ,  Paul Michael Farmwald ,  James M. Cleeves

    IPC分类号： G11C1700

    CPC分类号： H01L27/1021 ,  G11C11/5692 ,  G11C17/14 ,  G11C17/16 ,  G11C2213/71 ,  H01L27/0203 ,  H01L27/115

    摘要： An integrated circuit device includes a three-dimensional memory array and array terminal circuitry for providing to selected memory cells of the array a write voltage different from a read voltage. Neither voltage is necessarily equal to a VDD power supply voltage supplied to the integrated circuit. The write voltage, particularly if greater than VDD, may be generated by an on-chip voltage generator, such as a charge pump, which may require an undesirably large amount of die area, particularly relative to a higher bit density three-dimensional memory array formed entirely in layers above a semiconductor substrate. In several preferred embodiments, the area directly beneath a memory array is advantageously utilized to layout at least some of the write voltage generator, thus locating the generator near the selected memory cells during a write operation.

    摘要翻译： 集成电路器件包括三维存储器阵列和阵列端子电路，用于向阵列的选定存储单元提供不同于读取电压的写入电压。 两个电压都不一定等于提供给集成电路的VDD电源电压。 特别是如果大于VDD的写入电压可以由片上电压发生器（例如电荷泵）产生，其可能需要不期望的大量管芯面积，特别是相对于较高位密度的三维存储器阵列 完全以半导体衬底上的层形成。 在几个优选实施例中，存储器阵列正下方的区域有利地用于布置写入电压发生器中的至少一些，从而在写入操作期间将发生器定位在选定的存储器单元附近。

    RANDOM DELAY GENERATION FOR THIN-FILM TRANSISTOR BASED CIRCUITS
    77.
    发明申请
    RANDOM DELAY GENERATION FOR THIN-FILM TRANSISTOR BASED CIRCUITS 审中-公开
    基于薄膜晶体管的电路的随机延迟生成

    公开(公告)号：US20140323035A1

    公开(公告)日：2014-10-30

    申请号：US14328187

    申请日：2014-07-10

    申请人： Vivek SUBRAMANIAN ,  Mingming MAO ,  Zhigang WANG

    发明人： Vivek SUBRAMANIAN ,  Mingming MAO ,  Zhigang WANG

    IPC分类号： H04B1/04 ,  H01L21/66 ,  H03B5/12 ,  H04H20/16

    CPC分类号： H04B1/04 ,  G06K7/0008 ,  G06K7/10059 ,  G06K19/0723 ,  H01L22/20 ,  H01L2924/0002 ,  H03B5/1203 ,  H03K3/0315 ,  H03K3/033 ,  H03K3/355 ,  H03K5/13 ,  H03K5/133 ,  H04H20/16 ,  H01L2924/00

    摘要： Circuits and circuit elements configured to generate a random delay, a monostable oscillator, circuits configured to broadcasting repetitive messages wireless systems, and methods for forming such circuits, devices, and systems are disclosed. The present invention advantageously provides relatively low cost delay generating circuitry based on TFT technology in wireless electronics applications, particularly in RFID applications. Such novel, technically simplified, low cost TFT-based delay generating circuitry enables novel wireless circuits, devices and systems, and methods for producing such circuits, devices and systems.

    摘要翻译： 被配置为产生随机延迟的电路和电路元件，单稳态振荡器，被配置为广播重复消息无线系统的电路，以及用于形成这种电路，装置和系统的方法。 本发明有利地提供了在无线电子应用中特别是RFID应用中基于TFT技术的相对较低成本的延迟产生电路。 这种新颖的，技术上简化的，低成本的基于TFT的延迟产生电路实现了新颖的无线电路，设备和系统以及用于生产这样的电路，设备和系统的方法。