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    Asymmetric epitaxy and application thereof
    72.
    发明授权
    Asymmetric epitaxy and application thereof 有权
    不对称外延及其应用

    公开(公告)号：US07989297B2

    公开(公告)日：2011-08-02

    申请号：US12614699

    申请日：2009-11-09

    申请人： Haizhou Yin ,  Xinhui Wang ,  Kevin K. Chan ,  Zhibin Ren

    发明人： Haizhou Yin ,  Xinhui Wang ,  Kevin K. Chan ,  Zhibin Ren

    IPC分类号： H01L21/00

    CPC分类号： H01L21/26586 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/66659 ,  H01L29/7835

    摘要： The present invention provides a method of forming asymmetric field-effect-transistors. The method includes forming a gate structure on top of a semiconductor substrate, the gate structure including a gate stack and spacers adjacent to sidewalls of the gate stack, and having a first side and a second side opposite to the first side; performing angled ion-implantation from the first side of the gate structure in the substrate, thereby forming an ion-implanted region adjacent to the first side, wherein the gate structure prevents the angled ion-implantation from reaching the substrate adjacent to the second side of the gate structure; and performing epitaxial growth on the substrate at the first and second sides of the gate structure. As a result, epitaxial growth on the ion-implanted region is much slower than a region experiencing no ion-implantation. A source region formed to the second side of the gate structure by the epitaxial growth has a height higher than a drain region formed to the first side of the gate structure by the epitaxial growth. A semiconductor structure formed thereby is also provided.

    摘要翻译： 本发明提供了形成非对称场效应晶体管的方法。 所述方法包括在半导体衬底的顶部上形成栅极结构，所述栅极结构包括栅极叠层和邻近所述栅极堆叠的侧壁的间隔物，并且具有与所述第一侧相对的第一侧和第二侧; 从衬底中的栅极结构的第一侧进行成角度的离子注入，从而形成与第一侧相邻的离子注入区域，其中栅极结构防止成角度的离子注入到达邻近第二侧的衬底 门结构; 以及在栅极结构的第一和第二侧在衬底上进行外延生长。 结果，在离子注入区域上的外延生长比经历无离子注入的区域慢得多。 通过外延生长形成到栅极结构的第二侧的源极区域的高度高于通过外延生长形成于栅极结构的第一侧的漏极区域的高度。 还提供了由此形成的半导体结构。

    SELF-ALIGNED WELL IMPLANT FOR IMPROVING SHORT CHANNEL EFFECTS CONTROL, PARASITIC CAPACITANCE, AND JUNCTION LEAKAGE
    74.
    发明申请
    SELF-ALIGNED WELL IMPLANT FOR IMPROVING SHORT CHANNEL EFFECTS CONTROL, PARASITIC CAPACITANCE, AND JUNCTION LEAKAGE 有权
    用于改善短路通道效应控制，对准电容和接头泄漏的自对准井

    公开(公告)号：US20110073961A1

    公开(公告)日：2011-03-31

    申请号：US12568287

    申请日：2009-09-28

    申请人： Robert H. Dennard ,  Brian J. Greene ,  Zhibin Ren ,  Xinlin Wang

    发明人： Robert H. Dennard ,  Brian J. Greene ,  Zhibin Ren ,  Xinlin Wang

    IPC分类号： H01L29/78 ,  H01L21/336

    CPC分类号： H01L29/66772 ,  H01L21/26586 ,  H01L21/823814 ,  H01L29/105 ,  H01L29/66492 ,  H01L29/66537 ,  H01L29/66545 ,  H01L29/66659 ,  H01L29/7848 ,  H01L29/78654 ,  H01L29/78696

    摘要： A method of forming a self-aligned well implant for a transistor includes forming a patterned gate structure over a substrate, including a gate conductor, a gate dielectric layer and sidewall spacers, the substrate including an undoped semiconductor layer beneath the gate dielectric layer and a doped semiconductor layer beneath the undoped semiconductor layer; removing portions of the undoped semiconductor layer and the doped semiconductor layer left unprotected by the patterned gate structure, wherein a remaining portion of the undoped semiconductor layer beneath the patterned gate structure defines a transistor channel and a remaining portion of the doped semiconductor layer beneath the patterned gate structure defines the self-aligned well implant; and growing a new semiconductor layer at locations corresponding to the removed portions of the undoped semiconductor layer and the doped semiconductor layer, the new semiconductor layer corresponding to source and drain regions of the transistor.

    摘要翻译： 形成用于晶体管的自对准阱注入的方法包括在衬底上形成图案化栅极结构，该衬底包括栅极导体，栅极电介质层和侧壁间隔物，所述衬底包括在栅极介电层下面的未掺杂的半导体层，以及 未掺杂的半导体层下面的掺杂半导体层; 去除未图示的栅极结构保护的未掺杂半导体层和掺杂半导体层的部分，其中在图案化栅极结构下面的未掺杂半导体层的剩余部分限定晶体管沟道，并且掺杂半导体层的图案化下面的掺杂半导体层的剩余部分 栅极结构定义了自对准阱植入物; 以及在对应于未掺杂半导体层和掺杂半导体层的去除部分的位置处生长新的半导体层，新的半导体层对应于晶体管的源极和漏极区域。

    STRUCTURE AND METHOD OF FABRICATING FINFET
    75.
    发明申请
    STRUCTURE AND METHOD OF FABRICATING FINFET 有权
    FINFET的结构和方法

    公开(公告)号：US20100244103A1

    公开(公告)日：2010-09-30

    申请号：US12413836

    申请日：2009-03-30

    申请人： Kevin K. Chan ,  Zhibin Ren ,  Xinhui Wang

    发明人： Kevin K. Chan ,  Zhibin Ren ,  Xinhui Wang

    IPC分类号： H01L29/772 ,  H01L21/461 ,  H01L21/38

    CPC分类号： H01L21/823821 ,  H01L29/66803

    摘要： A CMOS FinFET device and a method of manufacturing the same using a three dimensional doping process is provided. The method of forming the CMOS FinFET includes forming fins on a first side and a second side of a structure and forming spacers of a dopant material having a first dopant type on the fins on the first side of the structure. The method further includes annealing the dopant material such that the first dopant type diffuses into the fins on the first side of the structure. The method further includes protecting the first dopant type from diffusing into the fins on the second side of the structure during the annealing.

    摘要翻译： 提供了一种使用三维掺杂工艺的CMOS FinFET器件及其制造方法。 形成CMOS FinFET的方法包括在结构的第一侧和第二侧上形成翅片，并且在结构的第一侧的翅片上形成具有第一掺杂剂类型的掺杂剂材料的间隔物。 该方法还包括退火掺杂剂材料，使得第一掺杂剂类型扩散到结构的第一侧上的翅片。 该方法还包括在退火期间保护第一掺杂剂类型不扩散到结构的第二侧上的翅片。

    BODY CONTACTS FOR FET IN SOI SRAM ARRAY
    76.
    发明申请
    BODY CONTACTS FOR FET IN SOI SRAM ARRAY 有权
    用于SOI SRAM阵列中的FET的身体接触

    公开(公告)号：US20100207213A1

    公开(公告)日：2010-08-19

    申请号：US12707191

    申请日：2010-02-17

    申请人： Yue Tan ,  Zhibin Ren ,  Richard A. Wachnik ,  Haining S. Yang

    发明人： Yue Tan ,  Zhibin Ren ,  Richard A. Wachnik ,  Haining S. Yang

    IPC分类号： H01L27/12 ,  H01L21/86

    CPC分类号： H01L27/1203 ,  H01L21/743 ,  H01L21/84 ,  H01L27/11 ,  H01L27/1108 ,  H01L29/7833 ,  H01L29/7841

    摘要： Contact with a floating body of an FET in SOI may be formed in a portion of one of the two diffusions of the FET, wherein the portion of the diffusion (such as N−, for an NFET) which is “sacrificed” for making the contact is a portion of the diffusion which is not immediately adjacent (or under) the gate. This works well with linked body FETs, wherein the diffusion does not extend all the way to BOX, hence the linked body (such as P−) extends under the diffusion where the contact is being made. An example showing making contact for ground to two NFETs (PG and PD) of a 6T SRAM cell is shown.

    摘要翻译： 与SOI中的FET的浮体接触可以形成在FET的两个扩散中的一个中的一个的一部分中，其中“牺牲”的扩散部分（例如N，用于NFET）用于制造 接触是不直接相邻（或在门下方）的扩散部分。 这与连接的主体FET工作良好，其中扩散不会一直延伸到BOX，因此连接体（例如P-）在形成接触的扩散下延伸。 示出了向6T SRAM单元的两个NFET（PG和PD）接地的示例。

    Buried Stress Isolation for High-Performance CMOS Technology
    78.
    发明申请
    Buried Stress Isolation for High-Performance CMOS Technology 失效
    埋地应力隔离用于高性能CMOS技术

    公开(公告)号：US20080185658A1

    公开(公告)日：2008-08-07

    申请号：US12099195

    申请日：2008-04-08

    申请人： MeiKei Ieong ,  Zhibin Ren ,  Haizhou Yin

    发明人： MeiKei Ieong ,  Zhibin Ren ,  Haizhou Yin

    IPC分类号： H01L27/08 ,  H01L21/8238

    CPC分类号： H01L29/7846 ,  H01L21/823807 ,  H01L21/823878 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/66772 ,  H01L29/78654 ,  H01L29/78696

    摘要： A field effect transistor (FET) comprises a substrate; a buried oxide (BOX) layer over the substrate; a current channel region over the BOX layer; source/drain regions adjacent to the current channel region; a buried high-stress film in the BOX layer and regions of the substrate, wherein the high-stress film comprises any of a compressive film and a tensile film; an insulating layer covering the buried high-stress film; and a gate electrode over the current channel region, wherein the high-stress film is adapted to create mechanical stress in the current channel region, wherein the high-stress film is adapted to stretch the current channel region in order to create the mechanical stress in the current channel region; wherein the mechanical stress comprises any of compressive stress and tensile stress, and wherein the mechanical stress caused by the high-stress film causes an increased charge carrier mobility in the current channel region.

    摘要翻译： 场效应晶体管（FET）包括衬底; 在衬底上的掩埋氧化物（BOX）层; BOX层上的当前通道区域; 源极/漏极区域与当前沟道区域相邻; BOX层中的埋置的高应力膜和衬底的区域，其中高应力膜包括任何压缩膜和拉伸膜; 覆盖埋置的高应力膜的绝缘层; 以及在电流通道区域上的栅电极，其中所述高应力膜适于在所述电流通道区域中产生机械应力，其中所述高应力膜适于拉伸所述电流通道区域，以便产生机械应力 当前通道区域; 其中机械应力包括任何压缩应力和拉伸应力，并且其中由高应力膜引起的机械应力导致当前通道区域中电荷载流子迁移率增加。

    UNIAXIAL STRAIN RELAXATION OF BIAXIAL-STRAINED THIN FILMS USING ION IMPLANTATION
    79.
    发明申请
    UNIAXIAL STRAIN RELAXATION OF BIAXIAL-STRAINED THIN FILMS USING ION IMPLANTATION 失效
    使用离子植入的双应变薄膜的单轴应变松弛

    公开(公告)号：US20080171426A1

    公开(公告)日：2008-07-17

    申请号：US11622524

    申请日：2007-01-12

    申请人： Zhibin Ren ,  Katherine L. Saenger ,  Haizhou Yin

    发明人： Zhibin Ren ,  Katherine L. Saenger ,  Haizhou Yin

    IPC分类号： H01L21/425

    CPC分类号： H01L21/26506 ,  H01L21/823807 ,  H01L29/78 ,  H01L29/7848 ,  Y10S438/938

    摘要： A method for achieving uniaxial strain on originally biaxial-strained thin films after uniaxial strain relaxation induced by ion implantation is provided. The biaxial-strained thin film receives ion implantation after being covered by a patterned implant block structure. The strain in the uncovered region is relaxed by ion implantation, which induces the lateral strain relaxation in the covered region. When the implant block structure is narrow (dimension is comparable to the film thickness), the original biaxial strain will relax uniaxially in the lateral direction.

    摘要翻译： 提供了一种通过离子注入诱发的单轴应变松弛之后在原始双轴应变薄膜上实现单轴应变的方法。 双轴应变薄膜在被图案化的植入物块结构覆盖之后接收离子注入。 未覆盖区域的应变通过离子注入而松弛，这引起覆盖区域的横向应变弛豫。 当植入物块结构窄（尺寸与膜厚度相当）时，原始双轴应变将在横向方向上单轴弛豫。

    METHOD AND STRUCTURE FOR ENHANCING BOTH NMOSFET AND PMOSFET PERFORMANCE WITH A STRESSED FILM
    80.
    发明申请
    METHOD AND STRUCTURE FOR ENHANCING BOTH NMOSFET AND PMOSFET PERFORMANCE WITH A STRESSED FILM 有权
    用于增强半导体场效应晶体管的NMOSFET和PMOSFET性能的方法和结构

    公开(公告)号：US20070122961A1

    公开(公告)日：2007-05-31

    申请号：US11560925

    申请日：2006-11-17

    申请人： Huilong Zhu ,  Jing Wang ,  Bruce Doris ,  Zhibin Ren

    发明人： Huilong Zhu ,  Jing Wang ,  Bruce Doris ,  Zhibin Ren

    IPC分类号： H01L21/8234 ,  H01L21/8238

    CPC分类号： H01L21/82385 ,  H01L21/823807 ,  H01L21/823835 ,  H01L21/823842 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/7833 ,  H01L29/7843

    摘要： A structure and method for making includes adjacent pMOSFET and nMOSFET devices in which the gate stacks are each overlain by a stressing layer that provides compressive stress in the channel of the pMOSFET device and tensile stress in the channel of the nMOSFET device. One of the pMOSFET or nMOSFET device has a height shorter than that of the other adjacent device, and the shorter of the two devices is delineated by a discontinuity or opening in the stressing layer overlying the shorter device. In a preferred method for forming the devices a single stressing layer is formed over gate stacks having different heights to form a first type stress in the substrate under the gate stacks, and forming an opening in the stressing layer at a distance from the shorter gate stack so that a second type stress is formed under the shorter gate stack.

    摘要翻译： 用于制造的结构和方法包括相邻的pMOSFET和nMOSFET器件，其中栅极叠层各自被在pMOSFET器件的沟道中提供压应力的应力层和nMOSFET器件的沟道中的拉伸应力覆盖。 pMOSFET或nMOSFET器件中的一个具有比其他相邻器件的高度更短的高度，并且两个器件中的较短的器件通过覆盖较短器件的应力层的不连续或开口来描绘。 在用于形成器件的优选方法中，在具有不同高度的栅极堆叠上形成单个应力层，以在栅极堆叠下的衬底中形成第一类型应力，并且在距离较短栅极堆叠一定距离处的应力层中形成开口 使得在较短的栅极堆叠下形成第二种类型的应力。