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公开(公告)号：US20050248411A1
公开(公告)日：2005-11-10
申请号：US11117768
申请日：2005-04-28
Applicant: Jun Cao , Afshin Momtaz
Inventor： Jun Cao , Afshin Momtaz
CPC classification number: H03L7/10 , H03L7/095 , Y10S331/02
Abstract: Method and circuitry for improving the accuracy and efficiency of a phase-locked loop. More specifically, the present invention relates to a method and device for monitoring the frequency discrepancy between two signals in conjunction with at least one data signal so as to improve the accuracy and efficiency of a phase-locked loop. In one embodiment of the present invention, two counters are used to check the frequency differential between a VCO signal and an external reference or input signal. An adjustable threshold is provided to determine whether the frequencies of the two signals are considered to be in a frequency-locked mode. A pair of flip-flops is used to minimize any erroneous detection of frequency discrepancy by validating two consecutive results of the frequency differential check. In addition, a data present signal is used to control the transition between the phase-locked mode and the frequency-locked mode to minimize the potential data loss.
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公开(公告)号：US20050128846A1
公开(公告)日：2005-06-16
申请号：US11027864
申请日：2004-12-31
Applicant: Afshin Momtaz , Xin Wang , Jun Cao , Armond Hairapetian , David Chung
Inventor： Afshin Momtaz , Xin Wang , Jun Cao , Armond Hairapetian , David Chung
CPC classification number: G06F5/10 , G06F2205/106
Abstract: Methods and circuitry for implementing high speed first-in first-out (FIFO) structures. In one embodiment, a FIFO is disclosed that allows the frequency of one clock, e.g., the write clock, to be different than (e.g., half) that of the other (read) clock. In another embodiment a FIFO is presented that can be set and/or reset asynchronously. Other embodiments are disclosed wherein the read and write pointers are effectively monitored to ensure proper timing relationship, to detect loss of clock as well as to detect other abnormal FIFO conditions.
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公开(公告)号：US20050122815A1
公开(公告)日：2005-06-09
申请号：US11027193
申请日：2004-12-30
Applicant: Afshin Momtaz , Xin Wang , Jun Cao , Armond Hairapetian , David Chung
Inventor： Afshin Momtaz , Xin Wang , Jun Cao , Armond Hairapetian , David Chung
CPC classification number: G06F5/10 , G06F2205/106
Abstract: Methods and circuitry for implementing high speed first-in first-out (FIFO) structures. In one embodiment, a FIFO is disclosed that allows the frequency of one clock, e.g., the write clock, to be different than (e.g., half) that of the other (read) clock. In another embodiment a FIFO is presented that can be set and/or reset asynchronously. Other embodiments are disclosed wherein the read and write pointers are effectively monitored to ensure proper timing relationship, to detect loss of clock as well as to detect other abnormal FIFO conditions.
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公开(公告)号：US20050117428A1
公开(公告)日：2005-06-02
申请号：US11027848
申请日：2004-12-31
Applicant: Afshin Momtaz , Xin Wang , Jun Cao , Armond Hairapetian , David Chung
Inventor： Afshin Momtaz , Xin Wang , Jun Cao , Armond Hairapetian , David Chung
CPC classification number: G06F5/10 , G06F2205/106
Abstract: Methods and circuitry for implementing high speed first-in first-out (FIFO) structures. In one embodiment, a FIFO is disclosed that allows the frequency of one clock, e.g., the write clock, to be different than (e.g., half) that of the other (read) clock. In another embodiment a FIFO is presented that can be set and/or reset asynchronously. Other embodiments are disclosed wherein the read and write pointers are effectively monitored to ensure proper timing relationship, to detect loss of clock as well as to detect other abnormal FIFO conditions.
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公开(公告)号：US06721380B2
公开(公告)日：2004-04-13
申请号：US09919636
申请日：2001-07-31
Applicant: Armond Hairapetian , Jun Cao , Afshin Momtaz
Inventor： Armond Hairapetian , Jun Cao , Afshin Momtaz
IPC: H03L708
Abstract: The present invention relates in general to integrated circuits, and in particular to method and circuitry for implementing an improved phase-locked loop (PLL) in complementary metal-oxide-semiconductor (CMOS) technology using current-controlled CMOS (C3MOS) logic. In an exemplary embodiment, a phase-locked loop includes a phase-frequency detector, a Gm cell block, a low pass filter and a voltage controlled oscillator. These various elements of the phase-locked loop are connected to one another in a fully differential manner, i.e., each element has an input and/or an output each having at least a differential signal. In one embodiment, each of these various elements of the phase-locked loop is implemented using C3MOS logic.
Abstract translation: 本发明一般涉及集成电路，特别涉及使用电流控制CMOS（C 3 MOS）的互补金属氧化物半导体（CMOS）技术中实现改进的锁相环（PLL）技术的方法和电路 ）逻辑。 在示例性实施例中，锁相环包括相位频率检测器，Gm单元块，低通滤波器和压控振荡器。 锁相环的这些各种元件以完全差分的方式相互连接，即每个元件具有至少具有差分信号的输入和/或输出。 在一个实施例中，使用C 3 MOS逻辑来实现锁相环的这些各种元件中的每一个。
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Patent Agency Ranking
公开(公告)号：US09281828B2
公开(公告)日：2016-03-08
申请号：US13158075
申请日：2011-06-10
Applicant: Mahyar Kargar , Siavash Fallahi , Namik Kocaman , Afshin Momtaz
Inventor： Mahyar Kargar , Siavash Fallahi , Namik Kocaman , Afshin Momtaz
CPC classification number: H03L7/0807 , H03L7/00 , H03L7/087 , H03L7/091 , H03L7/0991 , H03L7/113 , H03L2207/06 , H04L7/0004 , H04L7/033
Abstract: Embodiments for reference-less voltage controlled oscillator (VCO) calibration are provided. Embodiments include a VCO calibration module which uses one or more signals from a frequency detector to automatically select a proper VCO band and bring the VCO clock frequency close enough to the data rate. The VCO calibration module uses a calibration code to calibrate the VCO. In embodiments, the calibration code is determined using a frequency search scheme, which includes a discovery phase to determine the proper VCO band, and a binary search phase and a monitoring phase to select the calibration code that brings the VCO clock frequency closest to the data rate.
Abstract translation: 提供了无参考压控振荡器（VCO）校准的实施例。 实施例包括VCO校准模块，其使用来自频率检测器的一个或多个信号来自动选择适当的VCO频带并使VCO时钟频率接近于数据速率。 VCO校准模块使用校准代码校准VCO。 在实施例中，使用频率搜索方案来确定校准码，该频率搜索方案包括确定适当的VCO频带的发现阶段以及二进制搜索阶段和监视阶段，以选择使VCO时钟频率最接近数据的校准码 率。
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公开(公告)号：US08731098B2
公开(公告)日：2014-05-20
申请号：US12882739
申请日：2010-09-15
Applicant: Delong Cui , Afshin Momtaz , Jun Cao
Inventor： Delong Cui , Afshin Momtaz , Jun Cao
CPC classification number: H04L7/0091 , H04L7/0008
Abstract: A transmitting system includes a clock system and a data system. The clock system is configured to receive a clock having a first value and produce a control signal having a second, different value and an output clock having the first value. The data system is configured to receive data and the control signal and to align the data with the output clock, based on the control signal, to produce output data. The clock system includes a driver configured to produce the output clock, a divider configured to divide the received clock, and a phase interpolator configured to rotate the divided clock to produce the control signal. Also, the data is parallel data, and the data system includes a multiplexer configured to receive the parallel data and to use the control signal to serialize the parallel data as the aligned data and a driver configured to produce the output data.
Abstract translation: 发射系统包括时钟系统和数据系统。 时钟系统被配置为接收具有第一值的时钟并且产生具有第二不同值的控制信号和具有第一值的输出时钟。 数据系统被配置为基于控制信号接收数据和控制信号并使数据与输出时钟对准，以产生输出数据。 时钟系统包括配置成产生输出时钟的驱动器，被配置为对接收的时钟进行分频的分频器，以及被配置为旋转分频时钟以产生控制信号的相位内插器。 此外，数据是并行数据，并且数据系统包括被配置为接收并行数据并且使用控制信号将并行数据串行化为对准数据的多路复用器和被配置为产生输出数据的驱动器。
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公开(公告)号：US08618964B2
公开(公告)日：2013-12-31
申请号：US13207887
申请日：2011-08-11
Applicant: Afshin Momtaz , Namik Kocaman , Bharath Raghavan
Inventor： Afshin Momtaz , Namik Kocaman , Bharath Raghavan
IPC: H03M1/06
CPC classification number: H03F3/45475 , H03F3/45183 , H03F2203/45686
Abstract: According to one general aspect, a distributed threshold adjuster (DTA) may be interspersed between stages of a multistage amplifier to adjust the DC voltage of an input signal. The DTA may include an input signal terminal configured to receive the input signal. The DTA may also include a plurality of current sources configured to produce an adjustment current signal whose amperage is configured to be increased or decreased by fixed steps in order to adjust the DC voltage of the input signal. The DTA may include a control unit configured to selectively turn on or off the individual current sources of the plurality of current sources to select the amperage of the adjustment current signal. The DTA may further include an output terminal configured to produce an output signal, comprising a combination of the input signal and the adjustment current signal, to a stage of a multistage amplifier.
Abstract translation: 根据一个一般方面，分布式阈值调节器（DTA）可以分散在多级放大器的级之间，以调节输入信号的直流电压。 DTA可以包括被配置为接收输入信号的输入信号端子。 DTA还可以包括多个电流源，其被配置为产生调节电流信号，其安培数被配置为通过固定步长增加或减小，以便调节输入信号的直流电压。 DTA可以包括控制单元，其被配置为选择性地打开或关闭多个电流源的各个电流源，以选择调节电流信号的电流强度。 DTA还可以包括输出端子，其被配置为产生包括输入信号和调整电流信号的组合的输出信号到多级放大器的级。
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公开(公告)号：US08618835B2
公开(公告)日：2013-12-31
申请号：US13242643
申请日：2011-09-23
Applicant: Burak Catli , Ali Nazemi , Mahmoud Reza Ahmadi , Ullas Singh , Jun Cao , Afshin Momtaz
Inventor： Burak Catli , Ali Nazemi , Mahmoud Reza Ahmadi , Ullas Singh , Jun Cao , Afshin Momtaz
IPC: H03K19/0175
CPC classification number: H03K19/0013 , H03K19/018521
Abstract: An apparatus is disclosed for converting signals from one digital integrated circuit family to be compatible with another digital integrated circuit family. The apparatus includes a primary interface and a secondary interface to convert a differential output signal from one digital integrated circuit family for use as an input signal by another digital integrated circuit family. The primary and secondary interfaces include gain stages that are configurable to provide rail to rail voltage swings and are characterized as having single pole architectures. The secondary interface may be unterminated such that a substantially equal load is presented to both components of the differential output signal.
Abstract translation: 公开了用于将来自一个数字集成电路系列的信号转换为与另一数字集成电路系列兼容的装置。 该装置包括主接口和辅助接口，用于转换来自一个数字集成电路系列的差分输出信号，以用作另一数字集成电路系列的输入信号。 主接口和辅助接口包括可配置为提供轨至轨电压摆幅的增益级，并且其特征在于具有单极架构。 次级接口可以是未端接的，使得对差分输出信号的两个分量提供基本上相等的负载。
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公开(公告)号：US08451058B2
公开(公告)日：2013-05-28
申请号：US13166592
申请日：2011-06-22
Applicant: Delong Cui , Afshin Momtaz , Jun Cao
Inventor： Delong Cui , Afshin Momtaz , Jun Cao
CPC classification number: H03F3/16 , H03F1/42 , H03F3/195 , H03F3/45183 , H03F2200/336 , H03F2200/423 , H03F2203/45631 , H03F2203/45638 , H03F2203/45702 , H03F2203/45706
Abstract: There is presented a high bandwidth circuit for high-speed transceivers. The circuit may comprise an amplifier combining capacitor splitting, inductance tree structures, and various bandwidth extension techniques such as shunt peaking, series peaking, and T-coil peaking to support data rates of 45 Gbs/s and above while reducing data jitter. The inductance elements of the inductance tree structures may also comprise high impedance transmission lines, simplifying implementation. Additionally, the readily identifiable metal structures of inductors and t-coils, the equal partitioning of the load capacitors, and the symmetrical inductance tree structures may simplify transceiver implementation for, but not limited to, a clock data recovery circuit.
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